Vertical meander inductor for small core voltage regulators
AssigneeIntel Corporation
InventorsChristopher J. Jezewski, Kevin P. O'Brien
Life of this patent
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Abstract
Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.
Claims28
A semiconductor die, comprising:
- a substrate;
- an integrated circuit disposed on an active front surface of the substrate;
- and
- an inductor coupled to the integrated circuit, the inductor disposed conformal with an insulating layer disposed on, but not through, an essentially planar back surface of the substrate, wherein an uppermost surface of the insulating layer has an undulating topography, and wherein both an uppermost surface and a lowermost surface of the inductor have the undulating topography.
A semiconductor die, comprising:
- a substrate;
- an integrated circuit disposed on an active front surface of the substrate;
- and
- an inductor coupled to the integrated circuit, the inductor disposed on and conformal with an insulating layer disposed on and conformal with, but not through, a back surface of the substrate, wherein the back surface of the substrate has an undulating topography, wherein both an uppermost surface and a lowermost surface of the insulating layer have the undulating topography, and wherein both an uppermost surface and a lowermost surface of the inductor have the undulating topography.
A method of fabricating a semiconductor structure, the method comprising:
- forming an integrated circuit on an active front surface of a substrate;
- forming an insulating layer on, but not through, an essentially planar back surface of the substrate, wherein an uppermost surface of the insulating layer has an undulating topography;
- and
- forming an inductor coupled to the integrated circuit, the inductor formed conformal with the insulating layer, wherein both an uppermost surface and a lowermost surface of the inductor have the undulating topography.
A method of fabricating a semiconductor structure, the method comprising:
- forming an integrated circuit on an active surface of a substrate;
- forming an undulating topography on a back surface of the substrate;
- forming an insulating layer conformal with, but not through, the back surface of the substrate;
- and
- forming an inductor coupled to the integrated circuit, the inductor formed conformal with the insulating layer, wherein both an uppermost surface and a lowermost surface of the insulating layer have the undulating topography, and wherein both an uppermost surface and a lowermost surface of the inductor have the undulating topography.
A semiconductor die, comprising:
- a substrate;
- an integrated circuit disposed on an active surface of the substrate;
- and
- an inductor coupled to the integrated circuit, the inductor disposed above a back surface of the substrate opposite the active surface, the back surface having an undulating topography, wherein the undulating topography of the back surface is faceted, wherein both an uppermost surface and a lowermost surface of the inductor have the undulating topography.
Dependencies are inferred from the claim text.