High-voltage ESD protection device

A high-voltage ESD protection device, comprising a silicon controlled rectifier, a first PMOS transistor and an isolation high-voltage P-well for isolating the silicon controlled rectifier from the first PMOS transistor, wherein:

• the silicon controlled rectifier and the first PMOS transistor are formed on a P-type epitaxial layer of a silicon substrate;
• the silicon controlled rectifier comprises a high-voltage P-well and a high-voltage N-well adjacent to each other;
• a first N+ diffusion region and a first P+ diffusion region are formed in the high-voltage P-well;
• a second N+ diffusion region and a second P+ diffusion region are formed in the high-voltage N-well;
• the first PMOS transistor comprises an N-type buried layer and a low-voltage N-well formed in the N-type buried layer of the first PMOS;
• a gate of the first PMOS transistor is formed on a surface of the low-voltage N-well;
• a third P+ diffusion region and a fourth P+ diffusion region are formed in the low-voltage N-well of the first PMOS to serve as a source and a drain of the first PMOS transistor, respectively;
• the gate, the source and the N-type buried layer of the first PMOS transistor are shorted together and connected to an electrostatic terminal;
• the drain of the first PMOS transistor is shorted to the second N+ diffusion region and the second P+ diffusion region;
• the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal for dissipating an electrostatic discharge between the electrostatic terminal and the ground terminal.