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US 8,803,255 B2Granted
Gate electrode having a capping layer
AssigneeIntel Corporation
InventorsGilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
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Abstract
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.
Claims23
A non-planar semiconductor device, comprising:
- a substrate having a three-dimensional semiconductor body thereon;
- a monolayer of an oxide of the three-dimensional semiconductor body, the monolayer disposed directly on the three-dimensional semiconductor body;
- a high-k dielectric material layer disposed directly on the monolayer, the high-k dielectric material layer including a first portion of a capping layer in vacant sites therein, wherein the monolayer of the oxide of the three-dimensional semiconductor body includes an element not included in the high-k dielectric material layer;
- and
- a gate electrode disposed above the high-k dielectric material layer.
2 more elements
A non-planar semiconductor device, comprising:
- a substrate having a three-dimensional semiconductor body thereon;
- an ultra-thin transition oxide layer disposed on the three-dimensional semiconductor body, the ultra-thin transition oxide layer consisting essentially of a monolayer or less of an oxide of the three-dimensional semiconductor body;
- a high-k dielectric material layer disposed on the ultra-thin transition oxide layer, the high-k dielectric material layer being in a thermodynamically stable form and having a thickness approximately in the range of 5-25 Angstroms;
- a barrier layer disposed on the high-k dielectric material layer;
- a capping layer disposed on the barrier layer and comprising a material different than the barrier layer;
- and
- a gate electrode disposed above the capping layer and comprising a material different than the capping layer, wherein the gate electrode comprises a workfunction controlling metal, and the barrier layer is sufficiently thin so as to be transparent to the workfunction controlling metal of the gate electrode.
4 more elements
A non-planar semiconductor device, comprising:
- a substrate having a three-dimensional semiconductor body thereon;
- an ultra-thin transition oxide layer disposed on the three-dimensional semiconductor body, the ultra-thin transition oxide layer consisting essentially of a monolayer or less of an oxide of the three-dimensional semiconductor body;
- a high-k dielectric material layer disposed on the ultra-thin transition oxide layer, the high-k dielectric material layer essentially free from vacant sites and having a thickness approximately in the range of 5-25 Angstroms;
- a barrier layer disposed on the high-k dielectric material layer;
- a capping layer disposed on the barrier layer and comprising a material different than the barrier layer;
- and
- a gate electrode disposed above the capping layer and comprising a material different than the capping layer, wherein the gate electrode comprises a workfunction controlling metal, and the barrier layer is sufficiently thin so as to be transparent to the workfunction controlling metal of the gate electrode.
4 more elements
A non-planar semiconductor device, comprising:
- a substrate having a three-dimensional semiconductor body thereon;
- a high-k dielectric material layer disposed on an ultra-thin transition oxide layer disposed above the three-dimensional semiconductor body, the high-k dielectric material layer including a first portion of a capping layer in vacant sites therein;
- a barrier layer disposed on the high-k dielectric material layer;
- a second portion of the capping layer disposed on the barrier layer;
- and
- a gate electrode disposed above the capping layer.
3 more elements
Dependencies are inferred from the claim text.