Methods of forming replacement gate structures for NFET semiconductor devices and devices having such gate structures

A gate structure for an NFET device, comprising:

• a gate insulation layer comprised of a high-k insulating material formed on a semiconducting substrate;
• a first metal layer made of titanium nitride (TiN) positioned on and in contact with an upper surface of said gate insulation layer;
• a second metal layer made of tantalum nitride (TaN) positioned on and in contact with an upper surface of said first metal layer;
• a third metal layer made of titanium aluminum (TiAl) positioned on and in contact with an upper surface of said second metal layer;
• a fourth metal layer made of aluminum or TiAl3 positioned on and in contact with an upper surface of said third metal layer;
• a fifth metal layer made of titanium positioned on and in contact with an upper surface of said fourth metal layer;
• and
• an aluminum-containing layer positioned on and in contact with an upper surface of said fifth metal layer.

A gate electrode structure for a planar NFET device, consisting of:

• a gate insulation layer formed above a semiconducting substrate;
• a first metal layer made of titanium nitride (TiN) positioned on and in contact with an upper surface of said gate insulation layer, wherein said first metal layer has a thickness of about 1-2 nm;
• a second metal layer made of tantalum nitride (TaN) positioned on and in contact with an upper surface of said first metal layer, wherein said second metal layer has a thickness of about 1-2 nm;
• a third metal layer made of TiAl3 positioned on and in contact with an upper surface of said second metal layer, wherein said third metal layer has a thickness of about 10 nm;
• a fourth metal layer made of titanium (Ti) positioned on and in contact with an upper surface of said third metal layer, wherein said fourth metal layer has a thickness of at least about 5 nm;
• and
• an aluminum-containing layer positioned on and in contact with an upper surface of said fourth metal layer.

A gate electrode structure for a planar NFET device, consisting of:

• a gate insulation layer comprised of a high-k insulating material positioned on and in contact with an upper surface of a semiconducting substrate;
• a first metal layer made of titanium nitride (TiN) positioned on and in contact with an upper surface of said gate insulation layer, wherein said first metal layer has a thickness of about 1-2 nm;
• a second metal layer made of tantalum nitride (TaN) positioned on and in contact with an upper surface of said first metal layer, wherein said second metal layer has a thickness of about 1-2 nm;
• a third metal layer made of TiAl3 positioned on and in contact with an upper surface of said second metal layer, wherein said third metal layer has a thickness of about 10 nm;
• a fourth metal layer made of titanium (Ti) positioned on and in contact with an upper surface of said third metal layer, wherein said fourth metal layer has a thickness of at least about 5 nm;
• and
• an aluminum-containing layer positioned on and in contact with an upper surface of said fourth metal layer.