Profile pre-shaping for replacement poly gate interlayer dielectric

An integrated circuit (IC), comprising:

• a semiconductor substrate having an upper surface with neighboring first and second gate electrodes disposed thereover;
• sidewall spacers formed on opposing sidewalls of the first and second gate electrodes;
• and
• a liner layer conformally disposed about opposite sides of the sidewall spacers, wherein an outer sidewall of the liner layer lies generally about a line traversing the upper surface of the substrate at an obtuse or right angle, the obtuse or right angle being measured from the upper surface of the semiconductor substrate to the outer sidewall of the liner layer without passing through the liner layer;
• wherein an outer sidewall of the sidewall spacer extends along a line that traverses the upper surface of the substrate at an acute angle, the acute angle measured from the upper surface of the substrate to the outer sidewall of the sidewall spacer without passing through the sidewall spacer.

An integrated circuit (IC), comprising:

• a semiconductor substrate having an upper surface with neighboring first and second gate electrodes disposed thereover;
• sidewall spacers formed on opposing sidewalls of the first and second gate electrodes;
• and
• a liner layer conformally disposed about opposite sides of the sidewall spacers, wherein an outer sidewall of the liner layer lies generally about a line traversing the upper surface of the substrate at an obtuse or right angle, the obtuse or right angle being measured from the upper surface of the semiconductor substrate to the outer sidewall of the liner layer without passing through the liner layer;
• and
• wherein an outer sidewall of the gate electrode extends along a line that traverses the upper surface of the semiconductor substrate at an acute angle, the acute angle measured from the upper surface of the semiconductor substrate to the outer sidewall of the gate electrode without passing through the gate electrode.

An integrated circuit (IC), comprising:

• a semiconductor substrate having an upper surface with a source region and drain region proximate thereto, wherein a channel region is disposed in the substrate between the source region and the drain region;
• a gate electrode disposed over the channel region and separated from the channel region by a gate dielectric, wherein upper outer edges of the gate electrode extend outward beyond corresponding lower outer edges of the gate electrode;
• sidewall spacers formed about opposing sidewalls of the gate electrode, wherein upper outer edges of the sidewall spacers extend outward beyond corresponding lower outer edges of the sidewall spacers;
• a liner layer disposed about opposite sides of the sidewall spacers, wherein an outer sidewall of the liner layer lies generally about a line traversing the upper surface of the substrate at an obtuse or right angle, the obtuse or right angle being measured from the upper surface of the semiconductor substrate to the outer sidewall of the liner layer without passing through the liner layer.

An integrated circuit (IC), comprising:

• a semiconductor substrate having an upper surface with a gate electrode disposed thereover;
• sidewall spacers formed on opposing sidewalls of the gate electrode;
• and
• a liner layer conformally disposed about outer sides of the sidewall spacers, wherein an outer sidewall of the liner layer lies generally about a line which traverses the upper surface of the substrate at an obtuse angle, the obtuse angle being measured from the upper surface of the semiconductor substrate to the outer sidewall of the liner layer without passing through the liner layer.