Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor

A complementary metal oxide semiconductor (CMOS) device comprising:

• a substrate including at least one first active region and at least one second active region, wherein each of the at least one first active region and each of the at least one second active region of the substrate are separated from one another by an isolation region positioned therebetween;
• an n-type semiconductor device on at least one of said at least one first active region of the substrate, the n-type semiconductor device comprising a first portion of a gate structure;
• a p-type semiconductor device on at least one of said second active region of the substrate, the p-type semiconductor device comprising a second portion of the gate structure, wherein electrical connectivity between the first portion of the gate structure and the second portion of the gate structure is provided by a connecting gate portion that is present on the isolation region, and wherein said connecting gate portion, said first portion of the gate structure and said second portion of the gate structure comprise a same continuous metal gate conductor layer;
• an interconnect in direct contact with an upper surface of the connecting gate portion of the gate structure that is present on the isolation region;
• and
• a dielectric cap layer located above the first portion and the second portion of the gate structure that is present on the least one first active region and the at least one second active region.