High voltage semiconductor device and method for fabricating the same

A method for fabricating a high voltage semiconductor device, comprising:

• providing a semiconductor substrate, having a first conductivity type;
• forming a drift region in a portion of the semiconductor substrate, wherein the drift region has a second conductivity type opposite to the first conductivity type;
• forming a gate structure and a dummy gate structure over the semiconductor substrate, wherein the gate structure partially covers the drift region, and the dummy gate structure is disposed over the drift region;
• forming a first insulating spacer and a pair of second insulating spacers, wherein the first insulating spacer is located between the gate structure and the dummy structure, and the second insulating spacers are respectively disposed over a sidewall of the dummy gate structure, and the drift region physically contacts the first insulating spacer and one of the second insulating spacers;
• performing an ion implanting process to form two doping regions in the semiconductor substrate adjacent to the second insulating spacers,
• wherein the doping regions have the second conductivity type, and one of the doping regions is formed in the drift region;
• and
• performing an annealing process.

A method for fabricating a high voltage semiconductor device, comprising:

• providing a semiconductor substrate, having a first conductivity type;
• forming a pair of drift regions in two different portions of the semiconductor substrate, wherein the drift regions have a second conductivity type opposite to the first conductivity type;
• forming a gate structure and a plurality of dummy gate structures over the semiconductor substrate, wherein the gate structure partially covers a portion of the drift regions and the dummy gate structures are respectively disposed over one of the drift regions;
• forming a first insulating spacer and a pair of second insulating spacers, wherein the first insulating spacer is located between the gate structure and the dummy structures, and the second insulating spacers are respectively disposed over a sidewall of the dummy gate structures, and each of the drift regions physically contacts the first insulating spacer and one of the second insulating spacers;
• performing an ion implanting process to form two doping regions in the semiconductor substrate adjacent to the second insulating spacers, wherein the doping regions have the second conductivity type, and the doping regions is respectively disposed in one of the drift regions;
• and
• performing an annealing process.