US 8,803,231 B2Granted

Trench MOS transistor and method of manufacturing the same

AssigneeSeiko Instruments Inc.

InventorsTomomitsu Risaki, Jun Osanai

Life of this patent

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Abstract

Trench portions (10) are formed in a well (5) in order to provide unevenness in the well (5). A gate electrode (2) is formed via an insulating film (7) on the upper surface and inside of the trench portions (10). A source region (3) is formed on one side of the gate electrode (2) in a gate length direction while a drain region (4) on another side. Both of the source region (3) and the drain region (4) are formed down to near the bottom portion of the gate electrode (2). By deeply forming the source region (3) and the drain region (4), current uniformly flows through the whole trench portions (10), and the unevenness formed in the well (5) increases the effective gate width to decrease the on-resistance of a semiconductor device 1 and to enhance the drivability thereof.

Claims5

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate;
a well of a first conductivity type which is formed on the semiconductor substrate, the well having a concave portion formed therein with varying depth in a gate width direction, a first flat portion extending away laterally from the concave portion in a first direction, and a second flat portion extending away from the concave portion in a second direction that is opposite to the first direction;
a gate electrode formed on an upper surface and inside of the concave portion via an insulating film, the gate electrode filling all of the concave portion;
a source region of a second conductivity type disposed on one side of the gate electrode and on the first flat portion, wherein the first flat portion is at least as deep into the well as a bottom surface of the gate electrode relative to an uppermost portion of the well, and wherein all of the source region has a uniform thickness in a longitudinal direction and a flat surface in a lateral direction;
and
a drain region of the second conductivity type disposed on another side of the gate electrode and on the second flat portion, wherein the second flat portion is at least as deep into the well as he bottom surface of the gate electrode relative to the uppermost portion of the well. and wherein all of the drain region having a uniform thickness in the longitudinal direction and a flat surface in the lateral direction.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/438,058Filed 3 Apr 2012 · division
Priority: JP 2007-0282947 Feb 2007
Published: US 2012/0187476 A126 Jul 2012
Granted: 12 Aug 2014
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 62/151
Source or drain regions of field-effect devices: of igfets
H10D 30/0221
Of FETs having insulated gates [IGFET]: having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or…
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/026
Of FETs having insulated gates [IGFET]: having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both…

Family

Application12/027,655Parent of this division · filed 7 Feb 2008
US 2012/0187476 A1Pre-grant publication · published 26 Jul 2012
US 8,168,494 B2Parent of this division
US 2008/0185639 A1Published application
US 8,803,231 B2This patent

From the US filing history. Foreign family members aren’t listed.