Nanowire transistor with surrounding gate
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
Claims21
An array of transistors comprising:
- a crystalline substrate;
- a plurality of transistors in rows and columns on the crystalline substrate, wherein row spacing between adjacent rows and column spacing between adjacent columns is determined by a minimum feature size (F) for a lithographic process;
- and
- each transistor in the transistor array comprises:
- a first source/drain region in the crystalline substrate;
- a semiconductor pillar on the crystalline substrate in contact with the first source/drain region, the semiconductor pillar having a cross-sectional dimension in a direction substantially parallel with a surface of the substrate that is less than the minimum feature size F;
- a second source/drain region in a top portion of the semiconductor pillar;
- a gate insulator around the semiconductor pillar;
- and
- a surrounding gate around and separated from the semiconductor pillar by the gate insulator.
An array of transistors comprising a plurality of transistors arranged in rows and columns, wherein a lithographic process is used to fabricate features used to form the transistors in the array, and wherein the lithographic process is constrained by a minimum feature size, each transistor in the transistor array comprising:
- a substrate;
- a first source/drain region in the substrate;
- a semiconductor pillar on the substrate in contact with the first source/drain region, the semiconductor pillar having a cross-sectional dimension less than the minimum feature size;
- a second source/drain region in a top portion of the semiconductor pillar;
- a gate insulator around the semiconductor pillar;
- and
- a surrounding gate around and separated from the semiconductor pillar by the gate insulator.
A transistor fabricated on a substrate using a lithographic process constrained by a minimum feature size, the transistor comprising:
- a first source/drain region in the substrate;
- a semiconductor pillar on the substrate in contact with the first source/drain region, the semiconductor pillar having a cross-sectional dimension less than the minimum feature size;
- a second source/drain region in a top portion of the semiconductor pillar;
- a gate insulator around the semiconductor pillar;
- and
- a surrounding gate around, and separated from, the semiconductor pillar by the gate insulator.
A transistor fabricated on a crystalline substrate using a lithographic process constrained by a minimum feature size, the transistor comprising:
- a first source/drain region in the crystalline substrate;
- a semiconductor pillar on the substrate in contact with the first source/drain region, the semiconductor pillar having cross-sectional dimensions less than the minimum feature size in both a first direction and a second direction, the second direction orthogonal to the first direction, wherein the first and second directions are substantially parallel with a surface of the substrate;
- a second source/drain region in a top portion of the semiconductor pillar, wherein the first and second source/drain regions define a channel region in the semiconductor pillar between the first and second source/drain regions;
- a gate insulator around the semiconductor pillar;
- and
- a surrounding gate around and separated from the semiconductor pillar by the gate insulator.
Dependencies are inferred from the claim text.