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US 8,803,224 B2Granted
MOS transistor suppressing short channel effect and method of fabricating the same
AssigneeSK hynix Inc.
InventorKyoung Bong Rouh
Life of this patent
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Abstract
A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.
Claims12
A semiconductor device comprising:
- a substrate;
- a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate;
- a gate insulating layer including:
- a lateral portion disposed on the channel region of the substrate,
- a first vertical extension joined to a first edge of the lateral portion, and
- a second vertical extension joined to a second edge of the lateral portion, the second edge being opposite the first edge,
- wherein the second vertical extention is longer than the first vertical extension, such that the gate insulating layer is asymmetric;
- and
- a gate electrode disposed over the first gate insulating layer.
6 more elements
A MOS transistor comprising:
- a substrate;
- a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate;
- a gate insulator including:
- a first gate insulating layer disposed on the channel region of the substrate,
- a second gate insulating layer having a specified depth from the surface of the substrate and being disposed between the first diffusion region and the channel region, and
- a third gate insulating layer having a specified depth from the surface of the substrate and being disposed between the second diffusion region and the channel region,
- wherein the depth of the third gate insulating layer is greater than the depth of the second gate insulating layer, such that the gate insulator is asymmetric;
- and
- a gate electrode disposed on the first gate insulating layer.
6 more elements
Dependencies are inferred from the claim text.