Three-dimensional semiconductor memory devices using direct strapping line connections

A memory device, comprising:

• a plurality of gate stacks extending in parallel on a substrate along a first direction, each of the gate stacks comprising a plurality of vertical channel regions;
• a plurality of insulation regions extending along the first direction and respectively disposed between adjacent ones of the gate stacks, the insulation regions having linear first portions having a first width and widened second portions having a second width greater than the first width;
• a common source region in the substrate underlying the insulation regions;
• respective conductive plugs passing through respective ones of the widened second portions of the insulation regions and electrically connected to the common source region;
• at least one bit line electrically connected to the vertical channel regions;
• and
• a plurality of strapping lines disposed on the conductive plugs and extending along the first direction, respectively disposed between the adjacent ones of the gate stacks,
• wherein top surfaces of the conducive plugs are located at a level higher than top surfaces of the vertical channel regions and lower than the at least one bit line.