Process of forming an electronic device including a control gate electrode, a semiconductor layer, and a select gate electrode

A process of forming an electronic device including a nonvolatile memory cell comprising:

• forming a first gate dielectric layer over a substrate;
• forming discontinuous storage elements over the first gate dielectric layer;
• forming a control gate electrode over the discontinuous storage elements;
• removing an exposed portion of the discontinuous storage elements after forming the control gate electrode;
• forming a first insulating spacer adjacent to the control gate electrode;
• selectively growing a semiconductor layer from an exposed portion of the substrate after forming the insulating spacer;
• forming a second gate dielectric layer over the semiconductor layer;
• forming a select gate electrode over the second gate dielectric layer;
• and
• forming a second insulating spacer partially over the control gate electrode and adjacent to the select gate electrode, wherein the control gate is between the second insulating spacer and the discontinuous storage elements,
• wherein:
• the semiconductor layer has a first surface lying farthest from the substrate, wherein the first surface lies at a first elevation;
• the control gate electrode has a second surface lying closest to the substrate, wherein the second surface lies at a second elevation;
• the first gate dielectric layer has a third surface lying farthest from the substrate, wherein the third surface lies at a third elevation;
• the first elevation lies between the second elevation and the third elevation;
• and
• the select gate electrode has a substantially triangular shape.

A process of forming an electronic device including a nonvolatile memory cell comprising:

• forming a charge storage stack over a substrate;
• forming a control gate electrode over the charge storage stack;
• forming a semiconductor layer over the substrate after forming the control gate electrode, wherein the semiconductor layer is spaced apart from the control gate electrode;
• forming a select gate electrode over the semiconductor layer, wherein forming the select gate electrode comprises:
• forming a select gate electrode layer over the control gate electrode, a first insulating spacer, and the semiconductor layer;
• and
• forming a second insulating spacer partially over the control gate electrode and adjacent to the spacer and the charge storage stack;
• and
• anisotropically etching the select gate electrode layer to form select gate electrode spacers, wherein at least one select gate electrode spacer serves as the select gate electrode for the nonvolatile memory cell.