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US 8,803,216 B2Granted
Memory cell system using silicon-rich nitride
AssigneesSpansion LLC, Advanced Micro Devices, Inc.
InventorsMeng Ding, Lei Xue, Mark Randolph, Chi Chang, Robert Bertram Ogle, Jr.
Life of this patent
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Abstract
A memory cell system including providing a substrate, forming a charge-storing stack having silicon-rich nitride on the substrate, and forming a gate on the charge-storing stack.
Claims20
A method of producing a memory cell system, said method comprising:
- providing a substrate;
- forming a charge-storing stack on said substrate, wherein said forming said charge-storing stack comprises:
- forming a first insulating layer,
- forming a tunneling layer directly on said first insulating layer,
- forming a first silicon-rich nitride charge-storing layer over said tunneling layer,
- forming at least a second silicon-rich nitride charge-storing layer directly on said first silicon-rich nitride charge storing layer, and
- forming a second insulating layer directly over said at least second silicon-rich nitride charge-storing layer;
- and
- forming a gate on said charge-storing stack.
6 more elements
A memory cell system comprising:
- a substrate;
- a charge-storing stack on said substrate, wherein said charge-storing stack comprises:
- a first insulating layer,
- a tunneling layer directly on said first insulating layer,
- a first silicon-rich nitride charge-storing layer over said tunneling layer,
- at least a second silicon-rich, nitride charge-storing layer directly on said first silicon-rich nitride charge-storing layer, and
- a second insulating layer formed directly over said at least second silicon-rich nitride charge-storing layer;
- and
- a gate on said charge-storing stack.
6 more elements
A method of producing a memory cell system, said method comprising:
- providing a substrate having at least one bitline;
- forming a first insulating layer on said substrate;
- forming a plurality of silicon-rich nitride charge-storing regions over said first insulating layer, wherein at least one of said plurality of silicon-rich nitride charge-storing regions is above and generally aligned with said at least one bitline, and each of said plurality of silicon-rich nitride charge-storing regions are laterally spaced apart from one another by a respective silicon nitride insulating region formed on said first insulating layer;
- forming a second insulating layer on said plurality of silicon-rich nitride charge-storing layer and said respective silicon nitride insulating region;
- and
- forming a gate on said second insulating layer.
3 more elements
A memory cell system comprising:
- a substrate having at least one bitline;
- a first insulating layer on said substrate;
- a plurality of silicon-rich nitride charge-storing regions over said first insulating layer, wherein at least one of said plurality of silicon-rich nitride charge-storing regions is above and generally aligned with said at least one bitline, and each of said plurality of silicon-rich nitride charge-storing regions are laterally spaced apart from one another by a respective silicon nitride insulating region formed on said first insulating layer;
- a second insulating layer on said plurality of silicon-rich nitride charge-storing regions and said respective silicon nitride insulating region;
- and
- a gate on said second insulating layer.
3 more elements
Dependencies are inferred from the claim text.