3D semiconductor device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Brian Cronquist, Deepak Sekar
Life of this patent
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Abstract
A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.
Claims30
A 3D semiconductor device, comprising:
- a first layer comprising first transistors;
- a first metal layer comprising aluminum or copper overlaying said first transistors;
- a second layer comprising second transistors;
- wherein said second layer is overlying said first metal layer, and
- wherein said second layer thickness is less than 200 nm,
- a first circuit comprising at least one of said first transistors,
- wherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure,
- wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, and
- wherein said least one input structure is adapted to connect an input to said device from an external device.
A 3D semiconductor device, comprising:
- a first layer comprising first transistors;
- a second layer comprising second transistors;
- wherein said second layer is overlying said first transistors, and
- wherein said second layer thickness is less than 200 nm, and
- wherein said second transistors are lithographically defined with less than 10 nm alignment error to said first transistors, and
- wherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure,
- wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, and
- wherein said least one input structure is adapted to connect an input to said device from an external device.
A 3D semiconductor device, comprising:
- a first layer comprising first transistors;
- a first metal layer comprising aluminum or copper overlaying said first transistors;
- and
- a second layer comprising second transistors;
- wherein said second layer is overlying said first metal layer, and
- wherein said second layer thickness is less than 200 nm, and
- wherein said second transistors are lithographically defined with less than 10 nm alignment error to said first transistors, and
- wherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure,
- wherein said second layer comprises a first active portion of said ESD protection structure and said first layer comprises a second active portion of said ESD protection structure, and
- wherein said least one input structure is adapted to connect an input to said device from an external device.
A 3D semiconductor device, comprising:
- a first layer comprising first transistors;
- a first metal layer comprising aluminum or copper overlaying said first transistors;
- and
- a second layer comprising second transistors;
- wherein said second layer is overlying said first metal layer, and
- wherein said second layer thickness is less than 200 nm, and
- wherein said device comprises an Electro-Static-Discharge (“ESD”) protection structure connected to at least one input structure, and
- wherein said second layer comprises a first active portion of said ESD protection structure, and said first layer comprises a second active portion of said ESD protection structure, and
- wherein said least one input structure is adapted to connect an input to said device from an external device, and
- wherein said first layer comprises at least one first circuit comprising said first transistors, said at least one first circuit is circumscribed by a first guard ring, and
- wherein said second layer comprises at least one second circuit comprising said second transistors, said at least one second circuit is circumscribed by a second guard ring, and
- wherein said second guard ring overlays said first guard ring.
Dependencies are inferred from the claim text.