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US 8,803,200 B2Granted
Access transistor with a buried gate
AssigneeAvalanche Technology, Inc.
InventorsKimihiro Satoh, Ebrahim Abedifard
Life of this patent
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Abstract
A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.
Claims19
A semiconductor device comprising:
- a semiconductor substrate having a mesa protruded therefrom;
- a drain and a source having a first type conductivity formed in a top portion and a bottom portion of said mesa, respectively;
- a channel region having a second type conductivity opposite to said first type formed between said source and said drain in said mesa;
- and
- a pair of gates formed on opposite sides of said channel region with a gate oxide interposed therebetween,
- wherein a pair of conductive channels are formed on opposite surfaces of said channel region adjacent to said pair of gates to allow substantially vertical flow of electric current between said source and said drain upon application of an appropriate voltage to said pair of gates.
3 more elements
A semiconductor device comprising:
- a plurality of memory cells, each of said plurality of memory cells including an access transistor and a memory element formed thereon, said access transistor comprising:
- a semiconductor substrate having a mesa protruded therefrom;
- a drain and a source having a first type conductivity formed in a top portion and a bottom portion of said mesa, respectively;
- a channel region having a second type conductivity opposite to said first type formed between said source and said drain in said mesa;
- and
- a pair of gates formed on opposite sides of said channel region with a gate oxide interposed therebetween,
- wherein a pair of conductive channels are formed on opposite surfaces of said channel region adjacent to said pair of gates to allow substantially vertical flow of electric current between said source and said drain upon application of an appropriate voltage to said pair of gates;
- a plurality of parallel bit lines with each bit line coupled to a respective row of said memory elements therebeneath in a first direction;
- and
- a plurality of parallel word lines with each word line coupled to a respectively row of said gates in a second direction perpendicular to said first direction.
7 more elements
Dependencies are inferred from the claim text.