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US 8,803,191 B2Granted
Systems, devices, and methods with integrable FET-controlled lateral thyristors
AssigneePakal Technologies, Inc.
InventorRichard A. Blanchard
Life of this patent
Estimating the term…
Abstract
Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup.
Claims20
A lateral thyristor device, comprising:
- a semiconductor layer which is positioned atop a layer of insulator, and is completely isolated by trenches on all sides thereof;
- a heavily-doped n+ emitter region at one end of a length of said semiconductor layer, and a lightly doped p-type base region adjacent said n+ emitter region, and a lightly doped n-type base region adjacent to said p-type base region but not to said n+ emitter region, and a heavily doped p+ emitter region which abuts said lightly doped n-type base region but not said lightly doped p-type base region nor said heavily doped n+ emitter;
- a first current carrying terminal contacting the n+ emitter region;
- a second current carrying terminal contacting the p+ emitter region, wherein the first current carrying terminal and the second current carrying terminal are located over a top surface of the semiconductor layer to form a lateral current-conduction device;
- a plurality of embedded gate electrodes spaced along the boundary between said p-type base region and said n-type emitter region, each said gate electrode being capacitively coupled to a portion of said p-type base region which is nearest said n+ emitter region;
- all of said gate electrodes which are adjacent said n+ emitter region being electrically connected together;
- wherein, when said gate inverts an adjacent portion of said p-type base region, a population of electrons, at a surface of said gate nearest said n-type base region provides a virtual emitter and thereby sustains latchup once conduction has been initiated;
- and
- wherein the combination of said n+ emitter and said p-type base, and the combination of said p+ emitter and said n-type base, are not jointly able to sustain latching if said gate has not inverted adjacent portions of said p-type base region.
6 more elements
A lateral thyristor device, comprising:
- a semiconductor layer which is positioned atop a layer of insulator, and is completely isolated by trenches on all sides thereof;
- a heavily-doped n+ emitter region at one end of a length of said semiconductor layer, and a lightly doped p-type base region adjacent said n+ emitter region, and a lightly doped n-type base region adjacent to said p-type base region but not to said n+ emitter region, and a heavily doped p+ emitter region which abuts said lightly doped n-type base region but not said lightly doped p-type base region nor said heavily doped n+ emitter;
- a plurality of embedded gate electrodes spaced along the boundary between said p-type base region and said n+ emitter region, each said gate electrode being capacitively coupled to a portion of said p-type base region which is nearest said n+ emitter region;
- all of said gate electrodes which are adjacent said n+ emitter region being electrically connected together by a surface layer of the same material;
- wherein said gate electrodes have a spacing which completely depletes through all of said p-type base material along a plane which separates said n-type emitter region from said n-type base region, when said gate electrode is driven negative;
- and
- wherein, when said gate inverts an adjacent portion of said p-type base region, a population of electrons, at a surface of said gate nearest said n-type base region, provides a virtual emitter and thereby sustains latchup once conduction has been initiated.
4 more elements
A lateral thyristor device, comprising:
- a semiconductor layer which is positioned atop a layer of insulator, and is completely isolated by trenches on all sides thereof;
- a heavily-doped n+ emitter region at one end of a length of said semiconductor layer, and a lightly doped p-type base region adjacent said n+ emitter region, and a lightly doped n-type base region adjacent to said p-type base region but not to said n+ emitter region, and a heavily doped p+ emitter region which abuts said lightly doped n-type base region but not said lightly doped p-type base region nor said heavily doped n+ emitter, and is located at the other end of said length of said semiconductor layer;
- a plurality of embedded gate electrodes spaced along the boundary between said p-type base region and said n-type emitter region, each said gate electrode extending through the full thickness of said p-type gate region and being capacitively coupled to a portion of said p-type base region which is nearest said n+ emitter region;
- all of said gate electrodes which are adjacent said n+ emitter region being electrically connected together;
- wherein said n+ emitter region is laterally contacted by a conductor, and has a doping profile which is vertically uniform;
- and wherein the junction between said n+ emitter and said p-type base, and the junction between said p+ emitter and said n-type base, will jointly latch to maintain conduction, during the on state, for as long as said gate inverts an adjacent part of said p-type base region.
3 more elements
Dependencies are inferred from the claim text.