Semiconductor device

A semiconductor device comprising:

• a first line;
• a second line;
• and
• a memory element, the memory element comprising:
• a capacitor;
• and
• a transistor, the transistor comprising:
• a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region;
• a gate electrode;
• and
• a first insulating layer over the gate electrode,
• wherein the channel formation region is provided over the gate electrode with the first insulating layer interposed therebetween,
• wherein one of a source and a drain of the transistor is electrically connected to the first line,
• wherein the other of the source and the drain of the transistor is electrically connected to one of terminals of the capacitor,
• wherein the other of the terminals of the capacitor is electrically connected to the second line,
• wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3, and
• wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A.

A semiconductor device comprising:

• a memory element, the memory element comprising:
• a transistor, the transistor comprising:
• a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region,
• wherein a carrier concentration in the crystalline oxide semiconductor layer is less than or equal to 5×1014 cm−3, and
• wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A.

A processor comprising:

• a timing control circuit;
• an instruction decoder operationally connected to the timing control circuit;
• a register array;
• an address logic and buffer circuit operationally connected to the register array;
• a data bus interface operationally connected to the register array;
• an arithmetic logic unit operationally connected to the register array;
• and
• an instruction register operationally connected to the instruction decoder and the register array,
• wherein at least one of the register array and the instruction register comprises a memory element,
• wherein the memory element comprising a transistor comprising a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region,
• and
• wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A.

A processor comprising:

• a register array;
• an arithmetic logic unit operationally connected to the register array;
• and
• an instruction register operationally connected to the arithmetic logic unit,
• wherein at least one of the register array and the instruction register comprises a memory element,
• wherein the memory element comprising a transistor comprising a crystalline oxide semiconductor layer comprising oxygen, indium, zinc and a metal other than indium and zinc, the crystalline oxide semiconductor layer including a channel formation region, and
• wherein a value of off-state current through the crystalline oxide semiconductor layer of the transistor is less than 1×10−13 A.