Creating an embedded reram memory from a high-K metal gate transistor structure

A method for creating an embedded resistive memory cell, comprising:

• forming a first electrode and a second electrode, wherein the second electrode is electrically isolated from the first electrode;
• forming a first dielectric layer that is included in a first stack of deposited layers, wherein the first stack is positioned relative to the first electrode such that the first electrode resides under the first stack;
• and
• forming a second dielectric layer that is simultaneously included in the first stack of deposited layers and included in a second stack of deposited layers, wherein the first stack and the second stack are positioned relative to the second electrode such that the second electrode resides under the first stack and extends from under the first stack to under the second stack.

A memory array, comprising

• a plurality of embedded resistive memory cells, wherein at least one of the embedded resistive memory cells comprises:
• (a.) a first stack of deposited layers comprising:
• a first dielectric layer, and
• a first portion of a second dielectric layer, wherein the second dielectric layer is a high-k dielectric layer and wherein the first portion of the second dielectric layer is disposed above the first dielectric layer;
• and
• (b.) a first electrode disposed under the first stack;
• (c.) a second stack of deposited layers comprising:
• a second portion of the second dielectric layer, and
• a metal layer disposed above the second dielectric layer;
• and
• (d.) a second electrode, wherein a first region of the second electrode is disposed under the first stack and a second region of the second electrode is disposed under the second stack, wherein the second electrode is electrically isolated from the first electrode.