Resistive memory element and related control method

A resistive memory array comprising:

• a plurality of resistive memory elements, each resistive memory element comprising:
• a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection;
• a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection;
• an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element, wherein:
• the top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises at least one of a corner of the top electrode projection and a corner of the bottom electrode projection, and
• an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane;
• a first level of bottom electrode programming lines electrically contacting some of the bottom electrode elements via a plurality of first bottom electrode contacts;
• a second level of bottom electrode programming lines electrically contacting some of the bottom electrode elements via a plurality of second bottom electrode contacts;
• the bottom electrode programming lines of the first level extending in a first direction and the bottom electrode programming lines of the second level extending in a second direction;
• a third level of bottom electrode programming lines electrically contacting some of the top electrode elements via a plurality of third top electrode contacts;
• a fourth level of bottom electrode programming lines electrically contacting some of the top electrode elements via a plurality of fourth top electrode contacts;
• the top electrode programming lines of the third level extending in a third direction and the top electrode programming lines of the fourth level extending in a fourth direction;
• a fifth level of top electrode programming lines electrically contacting some of the top electrode elements via a plurality of fifth top electrode contacts;
• and
• a sixth level of top electrode programming lines electrically contacting some of the bottom electrode elements via a plurality of sixth bottom electrode contacts.

A method comprising:

• providing a resistive memory array comprising a plurality of resistive memory elements, each resistive memory element comprising a top electrode element lying in a plane parallel to a reference plane, a bottom electrode element lying in a plane parallel to the reference plane, and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element, wherein a projection of the top electrode and a projection of the bottom electrode overlap in an overlapping region on the reference plane, wherein the resistive memory array further comprises:
• a first level of bottom electrode programming lines electrically contacting some of the bottom electrode elements via a plurality of first bottom electrode contacts,
• a second level of bottom electrode programming lines electrically contacting some of the bottom electrode elements via a plurality of second bottom electrode contacts,
• the bottom electrode programming lines of the first level extending in a first direction and the bottom electrode programming lines of the second level extending in a second direction,
• a third level of bottom electrode programming lines electrically contacting some of the top electrode elements via a plurality of third top electrode contacts,
• a fourth level of bottom electrode programming lines electrically contacting some of the top electrode elements via a plurality of fourth top electrode contacts, and
• the top electrode programming lines of the third level extending in a third direction and the top electrode programming lines of the fourth level extending in a fourth direction;
• the top electrode programming lines of the third level and the top electrode programming lines of the fourth level are perpendicularly crossing;
• and
• creating or disrupting at least one conductive filament in the active layer by applying a voltage to the top electrode and the bottom electrode.