Method of inhibiting wire collapse

A method of forming a 3D memory device, the method comprising:

• depositing material in a memory cell region and in a hookup region outside of the memory cell region;
• etching the material in the memory cell region to form lines and gaps;
• etching the material in the hookup region to form trenches between CMP dummies formed from the material;
• forming a flowable film in the memory cell region and in the hookup region, the flowable film substantially fills the gaps, the flowable film does not completely fill the trenches in the hookup region;
• forming a capping layer over the flowable film in the memory cell region and in the hookup region, the capping layer filling remaining portions of the trenches not filled by the flowable film;
• curing the flowable film after forming the capping layer resulting in a dielectric;
• planarizing the capping layer in the hookup region;
• removing the capping layer in the memory cell region to expose the material for memory cells;
• forming a conductive region over portions of the capping layer in the hookup region that are in the trenches and over the exposed material for memory cells in the memory cell region;
• etching the conductive region in the hookup region to form conductive wires, the etching removes portions of the capping layer in the trenches to form insulating lines below the conductive wires, each of the conductive wires is supported by an insulating line;
• etching the conductive region in the memory cell region to form word lines or bit lines, the word lines or bit lines are electrically connected to the conductive wires;
• and
• forming zias in the hookup region, the zias are electrically connected to the conductive wires, the zias are electrically coupled to drivers.

A method of forming a 3D memory device, the method comprising:

• depositing material for reversible resistivity memory cells in a memory cell region and in a hookup region outside of the memory cell region;
• etching the material in the memory cell region to form lines and gaps;
• etching the material in the hookup region to form trenches between CMP dummies formed from the material;
• depositing a flowable oxide film in the memory cell region and in the hookup region, the flowable oxide film substantially fills the gaps, the flowable oxide film does not completely fill the trenches in the hookup region;
• forming a capping layer over the flowable oxide film in the memory cell region and in the hookup region, the capping layer filling remaining portions of the trenches not filled by the flowable oxide film;
• planarizing the capping layer in the hookup region;
• removing the capping layer in the memory cell region to expose the material for memory cells;
• forming a conductive material over portions of the capping layer in the hookup region that are in the trenches and over the exposed material for memory cells in the memory cell region;
• etching the conductive material in the hookup region to form conductive wires, wherein the conductive wires for a given trench have a total pitch, the forming a flowable oxide film in the hookup region leaves a space in the given trench that is at least as wide as the pitch of the conductive wires;
• etching the conductive material in the memory cell region to form conductive lines, the conductive lines are electrically connected to the conductive wires.