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US 8,802,553 B2Granted
Method for mounting a semiconductor chip on a carrier
AssigneeInfineon Technologies AG
InventorsAlexander Heinrich, Konrad Roesl, Oliver Eichinger
Life of this patent
Estimating the term…
Abstract
A method includes providing a semiconductor chip having a first main surface and a layer of solder material deposited on the first main surface, wherein the layer of solder material has a roughness of at least 1 μm. The semiconductor chip is placed on a carrier with the first main surface of the semiconductor chip facing the carrier. The semiconductor chip is pressed on the carrier with a pressure of at least 1 Newton per mm2 of surface area of the first main surface and heat is applied to the solder material.
Claims24
A method, comprising:
- forming a layer of solder material on a semiconductor chip, the layer of solder material having a first main surface and a second main surface, the first main surface being adjacent the semiconductor chip and the second main surface comprising a rough surface;
- pressing the second main surface of the layer of solder material directly on a substantially smooth surface of a carrier at a first temperature below a melting temperature of the solder material;
- applying a second temperature to the layer of solder material, wherein applying the second temperature to the layer of solder material comprises heating the solder material to a temperature that is below the melting temperature of the solder material thereby forming intermetallic phases between a first portion of the layer of solder material and the substantially smooth surface of the carrier;
- and
- heating the layer of solder material to a third temperature that is higher than the melting temperature of the solder material but lower than a melting temperature of the intermetallic phases thereby melting a second portion of the layer of solder material.
2 more elements
A method, comprising:
- forming a layer of solder material on a semiconductor chip, the layer of solder material having a main surface with a roughness of at least 1 μm;
- placing the semiconductor chip directly on a leadframe with a substantially smooth surface at a first temperature below a melting temperature of the solder material such that the main surface of the layer of solder material faces the leadframe;
- applying a second temperature to the solder material after the placement of the semiconductor chip on the leadframe, wherein applying the second temperature to the solder material comprises forming intermetallic phases between a first portion of the layer of solder material and the substantially smooth surface of the leadframe;
- and
- heating the layer of solder material to a third temperature that is higher than the melting temperature of the solder material but lower than a melting temperature of the intermetallic phases thereby melting a second portion of the layer of solder material.
2 more elements
A method comprising:
- placing a chip on a carrier, the chip comprising a solder layer having a rough surface;
- forming intermetallic phases between a first portion of the solder layer and the carrier by applying a temperature to the carrier and the solder layer below a melting temperature of the solder layer;
- and
- forming an electrical connection by melting a second portion of the solder layer,
- wherein melting the second portion of the solder layer comprises not melting the first portion.
2 more elements
A method comprising:
- placing a chip on a carrier, the chip comprising a solder layer having a rough surface comprising peaks;
- forming a mechanical connection between the chip and the carrier by deforming portions of the peaks by applying a first temperature below a melting temperature of a solder material of the solder layer;
- forming intermetallic phases between a first region of the solder layer and a first region of the carrier by applying a second temperature below the melting temperature of the solder material;
- and
- forming an electrical connection by melting a second region of the solder layer by applying a third temperature above the melting temperature of the solder material but below a melting temperature of the intermetallic phases.
2 more elements
Dependencies are inferred from the claim text.