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US 8,802,517 B2Granted
Extreme high mobility CMOS logic
AssigneeIntel Corporation
InventorsSuman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
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Abstract
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
Claims12
An NMOS transistor, comprising:
- an indium phosphide (InP) substrate;
- an indium aluminum arsenide (InAlAs) buffer layer disposed above the InP substrate;
- a bottom barrier layer disposed above the InAlAs buffer layer;
- an indium arsenide (InAs) quantum well layer disposed above the bottom barrier layer;
- a top barrier layer disposed above the InAs quantum well layer;
- a gate stack disposed above the top barrier layer, the gate stack comprising:
- an aluminum oxide (Al2O3) high-k gate dielectric layer disposed above the top barrier layer;
- and
- a metal gate electrode disposed above the Al2O3high-k gate dielectric layer;
- and
- raised source and drain regions disposed above an etch stop layer disposed above the top barrier layer, the raised source and drain regions disposed on either side of the gate stack, wherein the raised source and drain regions are formed in an indium gallium arsenide (InGaAs) cap layer disposed above the etch stop layer.
8 more elements
A method of fabricating an NMOS transistor, the method comprising:
- forming an indium aluminum arsenide (InAlAs) buffer layer above an indium phosphide (InP) substrate;
- forming a bottom barrier layer above the InAlAs buffer layer;
- forming an indium arsenide (InAs) quantum well layer above the bottom barrier layer;
- forming a top barrier layer above the InAs quantum well layer;
- forming an indium phosphide (InP) etch stop layer above the top barrier layer;
- forming an indium gallium arsenide (InGaAs) cap layer above the InP etch stop layer;
- forming a trench in the InGaAs cap layer;
- forming a gate stack in the trench by forming an aluminum oxide (Al2O3) high-k gate dielectric layer and a metal gate electrode;
- and
- forming source and drain regions in the InGaAs cap layer, on either side of the trench.
7 more elements
Dependencies are inferred from the claim text.