Methods for controlling line dimensions in spacer alignment double patterning semiconductor processing

A method, comprising:

• forming a first mask layer over a semiconductor substrate, forming a second mask layer over the first mask layer, and forming a dummy layer over the second mask layer;
• patterning a plurality of dummy lines in the dummy layer by a first photolithographic process, the dummy lines having a first width and spaced apart by a first spacing distance and having a first pitch that includes the width of a dummy line and the spacing distance;
• depositing a dielectric material over the dummy lines;
• removing the dielectric material from a top surface of the dummy lines and from the spaces between the dummy lines to form sidewall spacers adjacent each side of the dummy lines;
• etching the dummy material from the sidewall spacers to form a plurality of dielectric spacer lines in parallel, each having a second width and having a second pitch;
• etching the second mask layer using the dielectric spacer lines as an etch mask, to form a plurality of outer lines that are temporary lines outside of a plurality of desired lines inside the temporary lines all in the second mask layer;
• performing a second photolithographic pattern to form a photoresist that covers the desired lines and covers a portion of at least two temporary lines in the second mask layer, and etch cutting through at least two of the temporary lines so that the at least two temporary lines disposed outside of the plurality of desired lines have a second width less than the first width;
• and
• etching the second mask layer and the first mask layer using the lines in the second mask layer as an etch mask, the first mask layer being at least partially removed beneath the temporary lines of the dielectric, to form a pattern of desired lines in the first mask layer.

A method for forming fins for a finFET transistor, comprising:

• providing a semiconductor substrate and forming a first mask layer, a second mask layer, and a dummy layer over the semiconductor substrate;
• using a first photolithographic patterning step, patterning a plurality of dummy lines in the dummy layer, the dummy lines having a first width and a first spacing distance and having a first pitch that is the sum of the first width and the first spacing distance;
• depositing a spacer material over the dummy lines;
• etching the spacer material from a top surface of the dummy lines and the space between the dummy lines to form sidewall spacer lines on either side of each of the dummy lines;
• etching the dummy lines from the spacer material to form spacer lines having a second width and a second spacing distance and having a second pitch that is less than the first pitch;
• etching the second mask layer to form lines in the second mask layer corresponding to the spacer lines in the spacer material;
• using a second photolithographic patterning step, patterning the lines in the second mask layer, cutting through a portion of a pair of temporary spacer lines in the second mask layer surrounding a plurality of desired lines so that following the cutting process, the pair of temporary lines have a width that is less than the second width of the desired lines;
• using the temporary lines and the desired spacer lines as an etch mask, etching the first and second mask layers with a non-selective etch, removing the second mask layer from areas corresponding to the temporary lines and forming desired lines in the first mask layer;
• and
• using the desired lines in the first and second mask layers as an etch mask, etching the semiconductor substrate to form semiconductor fins corresponding to each of the desired lines.