Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection

A method for clamping a gate-to-drain voltage of a semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source encompassed in a body region and a drain with a gate to control an electric current transmitted between the source and the drain, wherein the method further comprising:

• interconnecting a gate-to-drain (GD) clamp circuit between said gate and said drain by forming a plurality of back-to-back polysilicon diodes connected on a first side in series to a silicon diode comprising at least one doped column in said semiconductor substrate and connecting said back-to-back polysilicon diodes on a second side to a gate electrode through a gate resistor;
• and
• forming an end well under the ends of said at least one doped column, wherein the end well has the same conductivity type as the doped column and has a lower doping concentration than the doped column.