Parallelization of PLC programs for operation in multi-processor environments
AssigneeSiemens Aktiengesellschaft
InventorsArquimedes Martinez Canedo, Mohammad Abdullah Al Faruque, Mitchell Packer, Richard Freitag
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Abstract
A method of identifying and extracting functional parallelism from a PLC program has been developed that results in the ability of the extracted program fragments to be executed in parallel across a plurality of separate resources, and a compiler configured to perform the functional parallelism (i.e., identification and extraction processes) and perform the scheduling of the separate fragments within a given set of resources. The inventive functional parallelism creates a larger number of separable elements than was possible with prior dataflow analysis methodologies.
Claims11
A programmable logic controller (PLC) for executing a program written in one or more high-level functional languages, the controller comprising
- a plurality of resources for executing various portions of the program;
- and
- a compiler including a processor and non-transitory computer readable media containing instructions that, when executed by the processor, perform functional parallelism by:
- parsing the program into a plurality of program organization units (POUs);
- identifying blocks within the high-level functional languages of each POU that include one or more time delay functions that delay an output by one execution cycle, such that operations before and after the time delay functions can be executed in parallel;
- partitioning at least one of the blocks into first and second program fragments by separating at an identified time delay function, the first and second fragments comprising operations before and after the identified time delay function, respectively;
- and
- scheduling the first and second program fragments across separate processor resources of the plurality of resources to be executed concurrently.
A method of creating parallelism in a PLC program to provide parallel execution of various segments of the PLC program across a plurality of separate resources, the method comprising the steps of:
- performing a functional analysis on a high-level functional representation of the PLC program by identifying locations of time delay functions within the high-level functional representation between an input and an output of a function block, the time delay function delaying an output by one execution cycle;
- partitioning, using at least one memory coupled to at least one processor, the high-level functional representation of the PLC program into first and second program fragments by separating the representation at the identified locations into program fragments that may be executed concurrently in separate resources of the plurality of separate resources, the first and second program fragments comprising operations before and after the identified time delay.
Dependencies are inferred from the claim text.