Facilitating the design of a clock grid in an integrated circuit

A computer program product for facilitating design of a clock grid in an integrated circuit having a multi-level hierarchy, the computer program product comprising:

• a non-transitory tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
• generating a chip level virtual grid for the integrated circuit;
• propagating the chip level virtual grid across each level of the multi-level hierarchy;
• customizing the chip level virtual grid at a lowest level of the multi-level hierarchy to create a customized virtual grid for the lowest level of the multi-level hierarchy;
• iteratively, beginning with the lowest level of the multi-level hierarchy and ending with a highest level of the multi-level hierarchy:
• propagating the customized virtual grid for a current level of the multi-level hierarchy to a next level of the multi-level hierarchy;
• and
• customizing the chip level virtual grid at the next level of the multi-level hierarchy to create the customized virtual grid for the next level of the multi-level hierarchy;
• combining the customized virtual grid for the lowest level of the multi-level hierarchy and the customized virtual grid for each next level of the multi-level hierarchy to connect to a global clock grid for the integrated circuit.

A method for facilitating design of a clock grid in an integrated circuit having a multi-level hierarchy comprising a chip level having a plurality of units, each of the plurality of units having a plurality of macros:

• generating a chip level virtual grid for the chip level of the integrated circuit;
• propagating the chip level virtual grid across the multi-level hierarchy;
• customizing the chip level virtual grid at each of the plurality of macros to create a customized virtual grid for each macro;
• propagating the customized virtual grid for each of the plurality of macros to a corresponding one of the plurality of units;
• customizing the chip level virtual grid at each of the plurality of units to create the customized virtual grid for each of the plurality of units;
• propagating the customized virtual grid for each of the plurality of units to the chip level;
• and
• combining, by a computer, the customized virtual grid for the plurality of macros and the customized virtual grid for the plurality of units to form the clock grid for the integrated circuit.