Identifying candidate nets for buffering using numerical methods
AssigneeSynopsys, Inc.
InventorsAmir H. Mottaez, Mahesh A. Iyer
Life of this patent
Estimating the term…
Abstract
Systems and techniques are described for efficiently and accurately identifying candidate nets that would benefit from buffering. A buffering process can then be performed only on the identified candidate nets. Embodiments described herein can quickly and accurately identify nets for which performing buffering optimization would most likely waste computational time (so they can be skipped for the buffering transformation), thereby improving the overall performance of buffering optimization and overall physical synthesis optimization. Some embodiments use a buffer topology generating process to generate a buffer topology for a net and then use a numerical sizing process to size the buffers in the buffer topology and the driver gate.
Claims15
A method for performing buffering optimization, the method comprising:
- receiving a net that electrically connects an output of a driver gate with a set of sinks;
- determining, by computer whether or not buffering is expected to improve a delay of a path that passes through the net by at least using logical effort and parasitic delay values of the driver gate and logical effort and parasitic delay values of one or more buffers from a technology library, wherein said determining comprises:
- determining a first delay from an input of the driver gate to the set of sinks;
- determining optimal sizes for one or more candidate buffers that are being considered to be added to the net;
- determining a second delay from the input of the driver gate to the set of sinks assuming that the one or more candidate buffers with their optimal sizes have been added to the net;
- and
- determining whether or not buffering is expected to improve the delay of the path based on comparing the first delay with the second delay;
- in response to determining that buffering is expected to improve the delay of the path, performing buffering optimization on the net;
- and
- in response to determining that buffering is not expected to improve the delay of the path, skipping performing buffering optimization on the net.
A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to execute a method for performing buffering optimization, the method comprising:
- receiving a net that electrically connects an output of a driver gate with a set of sinks;
- determining whether or not buffering is expected to improve a delay of a path that passes through the net by at least using logical effort and parasitic delay values of the driver gate and logical effort and parasitic delay values of one or more buffers from a technology library, wherein said determining comprises:
- determining a first delay from an input of the driver gate to the set of sinks;
- determining optimal sizes for one or more candidate buffers that are being considered to be added to the net;
- determining a second delay from the input of the driver gate to the set of sinks assuming that the one or more candidate buffers with theft optimal sizes have been added to the net;
- and
- determining whether or not buffering is expected to improve the delay of the path based on comparing the first delay with the second delay;
- in response to determining that buffering is expected to improve the delay of the path, performing buffering optimization on the net;
- and
- in response to determining that buffering is not expected to improve the delay of the path, skipping performing buffering optimization on the net.
An apparatus, comprising:
- a processor;
- and
- a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the apparatus to execute a method for performing buffering optimization, the method comprising:
- receiving a net that electrically connects an output of a driver gate with a set of sinks;
- determining whether or not buffering is expected to improve a delay of a path that passes through the net by at least using logical effort and parasitic delay values of the driver gate and logical effort and parasitic delay values of one or more buffers from a technology library, wherein said determining comprises:
- determining a first delay from an input of the driver gate to the set of sinks;
- determining optimal sizes for one or more candidate buffers that are being considered to be added to the net;
- determining a second delay from the input of the driver gate to the set of sinks assuming that the one or more candidate buffers with their optimal sizes have been added to the net;
- and
- determining whether or not buffering is expected to improve the delay of the path based on
- comparing the first delay with the second delay;
- in response to determining that buffering is expected to improve the delay of the path,
- performing buffering optimization on the net;
- and
- in response to determining that buffering is not expected to improve the delay of the path, skipping performing buffering optimization on the net.
Dependencies are inferred from the claim text.