Method of analyzing interconnect for global circuit wires

A non-transitory computer-readable medium storing computer-executable instructions that when executed by a computer that includes a processor cause the computer to perform a method, the method comprising:

• for a target wire in a circuit design that comprises a plurality of wires, determining nearby wires that are parallel wires to the target wire, the determining including:
• identifying, using at least the processor, one or more parallel return paths for current from the target wire that forms a loop through the circuit design over one of the nearby parallel wires;
• calculating, using at least the processor, loop inductance and loop capacitance for each of the one or more return paths;
• and
• determining, using at least the processor, nearby wires that are non-parallel wires to the target wire, the determining including:
• identifying a non-parallel return path for current from the target wire that forms a loop through the circuit design over one or more of the non-parallel wires;
• calculating, using at least the processor, a capacitance value for the non-parallel return path;
• and
• calculating, using at least the processor, an estimated inductance value for the non-parallel return path by determining an inductance value at an infinite frequency based at least on the capacitance value for the non-parallel return path and scaling the inductance value at infinite frequency, wherein the infinite frequency is a frequency value where an impact of resistance on impedance becomes insignificant;
• generating, using at least the processor, a circuit model of the target wire that includes the loop inductance and the loop capacitance for each of the parallel return paths combined with the capacitance value for the non-parallel return path and the estimated inductance value from the non-parallel return path.

A computing system, comprising:

• a processor and a memory;
• a non-transitory computer-readable medium storing computer-executable instructions that when executed cause the processor to perform a method, the method comprising:
• for a target wire in a circuit design that comprises a plurality of wires:
• determining, using at least the processor, nearby wires that are parallel wires to the target wire in the circuit design, the determining including:
• calculating, using at least the processor, a first inductance value for the parallel wires;
• calculating, using at least the processor, a first capacitance value for the parallel wires;
• identifying non-parallel wires to the target wire and including:
• calculating, using the processor, a second capacitance value for the non-parallel wires;
• calculating, using the processor, an estimated inductance value for the non-parallel wires based on the second capacitance value;
• generating, using the processor, a circuit model for the target wire based at least in part by combining the first inductance value, the first capacitance value, the second capacitance value, and the estimated inductance value.