Designing analog circuits
AssigneeFujitsu Limited
InventorsSubodh M. Reddy, Toshiyuki Shibuya
Life of this patent
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Abstract
According to an aspect of an embodiment, a method of designing an analog circuit may include selecting multiple analog components for a circuit. The method may also include ordering the analog components. The method may also include determining at least one pareto-optimal design point for a parameter of each analog component. The pareto-optimal design point for each analog component may be based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components.
Claims20
A method of designing an analog circuit, the method comprising:
- determining a first pareto-optimal design point for a first analog component within a circuit based on a parameter of the first analog component and a performance metric for the first analog component using a first simulation of a low level modeling simulation type;
- determining, using a processor, a second pareto-optimal design point for a second analog component using a second simulation that excludes the first analog component, the second simulation being of the low level modeling simulation type used for the first simulation, the second analog component being coupled to the first analog component within the circuit and the second pareto-optimal design point being based on a parameter of the second analog component, a performance metric for the second analog component, and a first constraint resulting from the first pareto-optimal design point;
- and
- selecting a first value for the parameter of the first analog component at least partially based on the first pareto-optimal design point.
A method of designing an analog circuit, the method comprising:
- selecting a plurality of analog components for a circuit;
- ordering the analog components;
- determining, using a processor, at least one pareto-optimal design point for a parameter of each analog component using a simulation of a low-level model of each analog component, the simulation used for each of the respective analog components being of the same low level modeling simulation type, the pareto-optimal design point for each analog component being based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components;
- and
- characterizing a high-level model for each of the analog components based on the pareto-optimal design point of the respective analog component.
A processor configured to execute computer instructions stored in a computer-readable storage medium to cause a system to perform operations for designing an analog circuit, the operations comprising:
- selecting a plurality of analog components for a circuit;
- ordering the analog components;
- determining at least one pareto-optimal design point for a parameter of each analog component using a simulation of a low-level model of each analog component, the simulation used for each of the respective analog components being of the same low level modeling simulation type, the pareto-optimal design point for each analog component being based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components;
- and
- characterizing a high-level model for each of the analog components based on the pareto-optimal design point for the respective analog component.
Dependencies are inferred from the claim text.