Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnects

A method of determining a stage delay associated with an integrated circuit interconnect, comprising:

• extracting dimensions of a driver from a layout of said driver associated with said interconnect, wherein said driver is a cell for driving said interconnect;
• estimating a driver strength from said dimensions;
• estimating a driver delay based on said driver strength;
• estimating an interconnect delay based on extracted C and RC parameters associated with said interconnect;
• and
• estimating said stage delay based on said driver delay and said interconnect delay, wherein said method is executed by a computer.

An extraction tool, embodied in program code stored in a non-transitory computer readable storage media, said program code executable by a computer, for determining maximum and minimum stage delays associated with integrated circuit interconnects, comprising:

• a driver strength estimator configured to extract lengths and widths of drivers from a layout of said driver associated with said interconnects and estimate driver strengths therefrom, wherein said driver is a cell for driving said interconnect;
• a driver delay estimator coupled to said driver strength estimator and configured to estimate driver delays based on said driver strengths;
• an interconnect delay estimator configured to estimate interconnect delays based on extracted C and RC parameters associated with said interconnects;
• and
• a stage delay estimator coupled to said driver delay estimator and said interconnect delay estimator and configured to estimate said maximum and minimum stage delays based on said driver delays and said interconnect delays.