Integrated circuit layout design methodology with process variation bands
AssigneeMentor Graphics Corporation
InventorJuan Andres Torres Robles
Life of this patent
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Abstract
A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.
Claims39
A computer-implemented method of verifying an integrated circuit design, comprising:
- receiving a layout or portion thereof that defines one or more objects to be created with a photolithographic process;
- simulating, with a computer, how at least one of the one or more objects will be printed under two or more varying lithographic process conditions to produce edge displacement data for the at least one object under each of the two or more process conditions;
- combining the edge displacement data for the at least one object to generate one or more PV-bands;
- and
- analyzing the one or more PV-bands with one or more design rules to verify the integrated circuit design.
A computer readable storage device storing a number of instructions that when executed by a computer system, cause the computer system to perform a method of verifying a design represented by a layout or portion thereof that defines one or more objects to be created with a photolithographic process, the method comprising:
- simulating how at least one of the one or more objects will be printed under two or more varying lithographic process conditions to produce edge displacement data for the at least one object under each of the two or more process conditions;
- combining the edge displacement data for the at least one object to generate one or more PV-bands;
- and
- analyzing the one or more PV-bands with one or more design rules to verify the design.
A method of verifying an integrated circuit design, comprising:
- receiving, via a computer system, a layout or portion thereof that defines a number of objects to be created on a wafer with a photolithographic process;
- transmitting the layout received or portion thereof to a remote computer system that performs the acts of:
- simulating how at least one of the one or more objects will be printed on a wafer under two or more varying process conditions to produce edge displacement data for the at least one object under each of the two or more process conditions;
- combining the edge displacement data for the at least one object to generate one or more PV-bands;
- and
- analyzing the one or more PV-bands with one or more design rules to verify the integrated circuit design.
A computer-implemented method for verifying an integrated circuit layout that defines a number of objects to be created on a wafer with a photolithographic process comprising:
- receiving all or a portion of the integrated circuit layout defining one or more objects to be created on a wafer;
- determining, with a computer, maximum edge displacements with which the one or more objects will be printed on a wafer under each of two or more sets of varying photolithographic process conditions;
- combining the maximum edge displacements to produce a maximum combined edge displacement for at least one of the objects;
- and
- analyzing the maximum combined edge displacements of the objects with one or more design rules to verify the integrated circuit design.
A computer-readable storage device storing a number of instructions that when executed by a computer cause the computer to perform a method of verifying an integrated circuit design represented by all or a portion of an integrated circuit layout defining one or more objects to be created on a wafer, the method comprising:
- determining maximum edge displacements with which the one or more objects will be printed on a wafer under each of two or more sets of varying photolithographic process conditions;
- combining the maximum edge displacements to produce a maximum combined edge displacement for at least one of the objects;
- and
- analyzing the maximum combined edge displacements of the objects with one or more design rules to verify the integrated circuit design.
A computer-readable storage device storing a number of instructions stored thereon that can be executed by a computer to perform the acts of:
- reading data representing features of at least a portion of an integrated circuit layout;
- generating one or more manufacturability objects from the data, wherein at least one of the objects is generated by combining layout sensitivity data for one or more of the features across multiple process variations;
- performing operations on one or more of the objects using one or more operators;
- and
- generating analysis data using guidelines that describe relationships between one or more of the objects or between one or more of the objects and one or more of the operators.
A system comprising:
- one or more processors;
- one or more computer-readable storage media storing instructions that when executed by the processors cause the system to perform a method, the method comprising:
- simulating, with a computer, how one or more objects to be created with a photolithographic process will be printed under two or more varying photolithographic process conditions to produce edge displacement data for the one or more objects under each of the two or more process conditions;
- combining the edge displacement data to generate one or more PV-bands;
- and
- analyzing the one or more PV-bands with one or more design rules to verify the integrated circuit design.
A system comprising:
- one or more processors;
- one or more computer-readable storage media storing instructions that when executed by the processors cause the system to perform a method, the method comprising:
- determining maximum edge displacements with which one or more objects will be printed on a wafer under each of two or more sets of varying photolithographic process conditions;
- combining the maximum edge displacements to produce a maximum combined edge displacement for at least one of the objects;
- and
- analyzing the maximum combined edge displacements of the objects with one or more design rules to verify the integrated circuit design.
A computer-implemented method of verifying an integrated circuit design, the method comprising:
- generating one or more manufacturability objects from data representing features of at least a portion of an integrated circuit layout, wherein at least one of the objects is generated by combining layout sensitivity data for one or more of the features across multiple process variations;
- performing operations on one or more of the objects using one or more operators;
- and
- generating analysis data using guidelines that describe relationships between one or more of the objects or between one or more of the objects and one or more of the operators.
Dependencies are inferred from the claim text.