Convolutional interleaver for bursty memory access

A method of operating a data interleaver system comprising:

• accumulating N data values from a data input of a first integrated circuit to form a WRITE data burst;
• defining first WRITE addresses for the N data values in the WRITE data burst to an external memory of a second integrated circuit according to write address sets in a write address sequence;
• defining second WRITE addresses for duplicate memory locations associated with the same memory address of the write address sequence for different time sequences which are available during each WRITE data burst to enable the WRITE data burst;
• writing the WRITE data burst according to the write address sequence to the external memory, wherein writing the WRITE burst data comprises writing second data associated with a second time sequence to a selected memory location of a pair of duplicate memory locations, and wherein first data associated with a first time sequence is stored in the other memory location of the pair of duplicate memory locations;
• calculating READ addresses from the external memory for a READ data burst;
• reading the READ data burst from the external memory according to read address sets in a read address sequence, wherein the read address sequence is different than the write address sequence, and the second data associated with the second time sequence is read before the first data associated with the first time sequence;
• sending a first value of the READ data burst to a data output port of the first integrated circuit;
• storing remaining values of the READ data burst in local memory of the first integrated circuit;
• and
• reading the remaining values of the READ data burst from the local memory in a sequence according to the data interleaver system and providing the remaining values to the data output port.

A convolutional interleaver memory system comprising:

• a first integrated circuit (IC) having a WRITE buffer receiving data from a data channel of the first IC;
• a second integrated circuit having memory operable to be written to and read from in a burst fashion;
• an address generator of the first IC assigning memory locations in the memory for data in WRITE bursts according to settings of the convolutional interleaver memory system, wherein WRITE addresses associated with the memory of the second integrated circuit comprise duplicate memory locations associated with the same memory address of the write address sequence for different time sequences which are available during each WRITE burst of data to enable the WRITE burst of data according to write address sets in a write address sequence, and a selected memory location of a pair of duplicate memory locations is written with second data associated with a second time sequence during the WRITE burst of data, and first data associated with a first time sequence is stored in the other memory location of the pair of duplicate memory locations, wherein a read address sequence is different than the write address sequence, and the second data associated with the second time sequence is read before the first data associated with the first time sequence;
• and
• a local memory of the first IC storing at least N−1 data values of a READ burst from the memory according to read address sets in a read address sequence.