Data hardening to compensate for loss of data retention characteristics in a non-volatile memory

#Various embodiments of the present invention are generally directed to a method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells.

#In accordance with various embodiments, a controller is adapted to harden data stored in a first location of a memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations. The first and second locations may be one or more erasure blocks in a non-volatile memory array.

#These and other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion and the accompanying drawings.

#FIG. 1 provides a functional block representation of a data storage device constructed and operated in accordance with various embodiments of the present invention.

#FIG. 2 illustrates a number of memory cells of the array of FIG. 1, which in some embodiments are characterized as non-volatile Flash memory cells arranged in a NAND configuration.

#FIG. 3 is a schematic representation of a portion of the array of FIG. 1.

#The present disclosure generally relates to systems and methods for enhancing the reliability and integrity of data stored in a non-volatile memory. Solid state data storage devices can employ an array of memory cells to store data as a sequence of bits. Some types of memory cells, such as flash memory cells, can endure only a limited number of access operations before the cell structures begin to degrade. For example, some current generation flash memory cells that store multiple bits per cell (so-called MLC or multi-level cells) can only retain stored data for a few months after 5,000 access operations have taken place upon the cells.

#A variety of approaches have been proposed in the art to reduce the effects of operational wear on solid state memory cells. These approaches include the implementation of wear leveling techniques to uniformly distribute write and erase operations across the array, and the use of write deamplification techniques to reduce the number of write operations required to update and manage data stored to the array. While operable, there remains a need for improvements in the manner in which data are stored to an array having memory cells with advanced levels of wear.

#Various embodiments of the present invention are accordingly directed to an apparatus and method for hardening data stored in a memory array, such as but not limited to a flash memory array. As explained below, a variety of techniques may be employed to enhance the integrity and reliability of the stored data.