Methodology for correlated memory fail estimations

A method carried out by a computer system for estimating correlated failure distributions of memory array designs having different groupings of memory cells connected to peripheral logic elements, the method comprising:

• constructing memory unit models for the different groupings of memory cells based on at a plurality of parameters associated with the memory cells or the peripheral logic elements;
• establishing failure conditions of the memory unit models;
• calculating fail boundaries in terms of the plurality of parameters for the memory unit models by computing a center-of-gravity for corresponding failure conditions in a parametric space defined by the plurality of parameters, computing an anchor point which lies on a line from an origin of the parametric space to the center-of-gravity and is a closest failing point to the origin, and computing the given fail boundary as a line which passes through the anchor point and represents a linear fit with other failure points within a close distance of the anchor point;
• constructing memory array models for the memory array designs characterized by the fail boundaries;
• simulating operation of the memory array models repeatedly with random values of the plurality of parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation, wherein said simulating is repeated for a given memory array model until a corresponding standard deviation for memory unit failures of the given memory array model converges;
• calculating a mean and a variance of the memory unit failures for each of the memory array models;
• and
• identifying which of the memory array models has an optimal mean and variance.

A computer system comprising:

• one or more processors which process program instructions;
• a memory device connected to said one or more processors;
• program instructions residing in said memory device for estimating correlated failure distributions of memory array designs having different groupings of memory cells connected to peripheral logic elements, by constructing memory unit models for the different groupings of memory cells based on at least a first parameter associated with the memory cells and a second parameter associated with the peripheral logic elements;
• program instructions residing in said memory device for establishing failure conditions of the memory unit models;
• program instructions residing in said memory device for calculating fail boundaries in terms of the first and second parameters for the memory unit models based on the failure conditions;
• program instructions residing in said memory device for constructing memory array models for the memory array designs characterized by the fail boundaries;
• program instructions residing in said memory device for simulating operation of the memory array models repeatedly with random values of the first parameter assigned to the memory cells and random values of the second parameter assigned to the peripheral logic elements to identify memory unit failures for each simulated operation;
• and
• program instructions residing in said memory device for calculating a mean and a variance of the memory unit failures for each of the memory array models.

A computer program product comprising:

• a computer-readable storage device;
• and
• program instructions residing in said computer-readable storage device for estimating correlated failure distributions of memory array designs having different groupings of memory cells connected to peripheral logic elements, by
• constructing memory unit models for the different groupings of memory cells based on at least a first parameter associated with the memory cells and a second parameter associated with the peripheral logic elements,
• establishing failure conditions of the memory unit models,
• calculating fail boundaries in terms of the first and second parameters for the memory unit models based on the failure conditions,
• constructing memory array models for the memory array designs characterized by the fail boundaries,
• simulating operation of the memory array models repeatedly with random values of the first parameter assigned to the memory cells and random values of the second parameter assigned to the peripheral logic elements to identify memory unit failures for each simulated operation, and
• calculating a mean and a variance of the memory unit failures for each of the memory array models.