Clock control for reducing timing exceptions in scan testing of an integrated circuit

#Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains comprising multiple scan cells. The scan cells may be implemented, by way of example, utilizing respective flip-flops. The scan cells of a given scan chain are configurable to form a serial shift register for applying test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture outputs from other combinational logic of the integrated circuit.

#Scan testing of an integrated circuit may therefore be viewed as being performed in two repeating phases, namely, a scan shift phase in which the flip-flops of the scan chain are configured as a serial shift register for shifting in and shifting out of test patterns, and a scan capture phase in which the flip-flops of the scan chain capture combinational logic outputs. These two repeating scan test phases may be collectively referred to herein as a scan test mode of operation of the integrated circuit, or as simply a scan mode of operation. Outside of the scan test mode and its scan shift and scan capture phases, the integrated circuit may be said to be in a functional mode of operation. Other definitions of the scan test and functional operating modes may also be used.

#Integrated circuits commonly include multiple clock domains. In an integrated circuit of this type, different portions of the integrated circuit are provided with different clock signals via a clock distribution network. For scan testing purposes, several clock signals having a common frequency but associated with different clock domains may be synchronized with one another. This is often done to facilitate scan testing. However, in some situations this type of simplification can be problematic, in that clock delay defects detected for synchronized clock signals during scan testing may nonetheless permit proper functional operation of the integrated circuit, because the functional operation may not require these clock signals to be synchronous. This can reduce device yield when manufacturing integrated circuits, as the devices failing the scan testing may be rejected for clock delay defects that do not actually interfere with functional operation.

#FIG. 1 is a block diagram showing an integrated circuit testing system comprising a tester and an integrated circuit under test in one embodiment.

#FIG. 2 shows a more detailed view of a portion of the integrated circuit in the testing system of FIG. 1.

#FIGS. 3A, 3B, 3C and 3D illustrate the insertion of clock control elements in respective clock signal lines of a clock distribution network in the FIG. 2 integrated circuit.

#Embodiments of the invention will be illustrated herein in conjunction with exemplary testing systems and corresponding integrated circuits comprising scan test circuitry for supporting scan testing of additional circuitry of those integrated circuits. It should be understood, however, that embodiments of the invention are more generally applicable to any testing system or associated integrated circuit in which it is desirable to provide improved control of clock signals in a clock distribution network of the integrated circuit in a manner that reduces timing exceptions during scan testing.

#FIG. 1 shows an embodiment of the invention in which a testing system 100 comprises a tester 102 and an integrated circuit under test 104. The integrated circuit 104 comprises scan test circuitry 106 coupled to additional internal circuitry 108 that is subject to testing utilizing the scan test circuitry 106. The tester 102 stores scan data 110 associated with scan testing of the integrated circuit. Such scan data may correspond to test patterns provided by a test pattern generator 112. In other embodiments, at least a portion of the tester 102, such as the test pattern generator 112, may be incorporated into the integrated circuit 104. Alternatively, the entire tester 102 may be incorporated into the integrated circuit 104, as in a built-in self-test (BIST) arrangement.

#The test pattern generator 112 may be implemented as an automatic test pattern generator (ATPG), and may be viewed as an example of what is more generally referred to herein as a test generation tool.