Semiconductor devices and semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorsChi-sung Oh, Jung-sik Kim, Ho-cheol Lee, Jung-bae Lee
Life of this patent
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Abstract
Semiconductor devices configured to test connectivity of micro bumps including one or more micro bumps and a boundary scan test block for testing connectivity of the micro bumps by scanning data input to the micro bumps and outputting the scanned data. The semiconductor device may include a first chip including solder balls and at least one or more switches electrically coupled with the respective solder balls, and a second chip stacked on top of the first chip and electrically coupled with the switches in direct access mode, including micro bumps that input/output signals transmitted from/to the solder balls.
Claims22
A semiconductor device, comprising:
- at least one through electrode;
- at least one micro bump;
- and
- a boundary scan test block configured to test micro bump connectivity by scanning data input to the at least one micro bump and outputting the scanned data, the boundary scan test block includes a scan chain having a plurality of selection units and a plurality of flip-flops,
- wherein the plurality of selection units are connected in parallel with respect to the plurality of flip flops.
A semiconductor package, comprising:
- a first chip including at least one solder ball and at least one switch electrically connected to the at least one solder ball;
- a second chip stacked on the first chip and electrically connected to the at least one switch in a direct access mode, the second chip including at least one micro bump configured to input/output signals transmitted from/to the at least one solder ball;
- and
- a semiconductor device including at least one boundary scan test block configured to test micro bump connectivity, the at least one boundary scan test block includes a scan chain having a plurality of selection units and a plurality of flip-flops,
- wherein the plurality of selection units are connected in parallel with respect to the plurality of flip flops.
A semiconductor package, comprising:
- a first chip including at least one solder ball and at least one switch electrically connected to the at least one solder ball;
- a second chip stacked on the first chip and electrically connected to the at least one switch in a direct access mode, the second chip including at least one micro bump configured to input/output signals transmitted from/to the at least one solder ball;
- and
- a semiconductor device including at least one through electrode, at least one micro bump and at least one boundary scan test block configured to test micro bump connectivity by scanning data input to the micro bump of the semiconductor device and outputting the scanned data, a boundary scan test block configured to test micro bump connectivity by scanning data input to the at least one micro bump and outputting the scanned data,
- the at least one boundary scan test block includes a scan chain having a plurality of selection units and a plurality of flip-flops,
- wherein the plurality of selection units are connected in parallel with respect to the plurality of flip flops.
Dependencies are inferred from the claim text.