Arithmetic processing apparatus and method of controlling arithmetic processing apparatus

An arithmetic processing apparatus for connection to a memory device that stores data, the arithmetic processing apparatus comprising;

• an instruction processing unit to output a memory access request;
• a cache memory to store part of data stored in the memory device in plural cache lines provided for a plurality of ways;
• an error detecting unit to detect an error occurring in one of the cache lines;
• an error-way register to store error-way identification information indicative of a way to which a cache line having a first error belongs when the error detecting unit detects the first error occurring in the cache line that is one of the cache lines;
• an error-word-address register to store an error word address that is a word address of the cache line having the first error;
• an error-column-address register to store an error column address that is a column address of the cache line having the first error;
• a way comparing unit to compare way identification information of a cache line to be accessed with the error-way identification information;
• a word comparing unit to compare a word address of the cache line to be accessed with the error word address;
• a column comparing unit to compare a column address of the cache line to be accessed with the error column address;
• and
• a control unit to disable all cache lines sharing a failed word line in response to results of comparisons made by the way comparing unit, the word comparing unit, and the column comparing unit when the error detecting unit detects a second error occurring in any one of the cache lines in response to the memory access request after the occurrence of the first error.