System on a chip (SOC) debug controllability

A method comprising:

• monitoring for specified conditions in a plurality of IP blocks in an integrated circuit, wherein the plurality of IP blocks include at least one non-CPU block;
• detecting one or more of the specified conditions in the plurality of IP blocks;
• transmitting an indication of the detecting to a debug controller in the integrated circuit;
• and
• responsive to the indication, the debug controller halting the plurality of IP blocks in the integrated circuit, wherein the debug controller is programmable to delay the halting by a programmable delay from receiving the indication.

A method comprising:

• monitoring for specified conditions in a plurality of component blocks in an integrated circuit, wherein the plurality of component blocks include a central processing unit (CPU) block and at least one non-CPU block;
• detecting one or more of the specified conditions in the plurality of component blocks;
• transmitting an indication of the detecting to a debug controller in the integrated circuit;
• and
• responsive to the indication, the debug controller delaying for a programmable time and then halting the plurality of component blocks in the integrated circuit.

A non-transitory computer accessible storage medium storing a plurality of instructions which, when executed:

• program a plurality of local debug control units to monitor respective IP blocks of a system on a chip (SOC) for selected debug events, wherein the debug events that are detectable vary dependent on the functionality implemented by each IP block, and wherein at least one of the IP blocks is a central processing unit (CPU) complex including one or more processors and at least one other IP block is not a CPU complex;
• program a delay in an SOC debug control unit that is coupled to the plurality of local debug control units, wherein the SOC debug control unit is coupled to receive an indication from the plurality of local debug control units that a selected debug event has been detected, and wherein the SOC debug control unit is configured to halt the SOC responsive to the detection of the selected debug event and further responsive to the delay expiring after the detection of the selected debug event;
• detect that the SOC has halted responsive to detection of the selected debug events;
• scan out a state of the SOC;
• and
• display the state of the SOC to a user.

An integrated circuit comprising:

• a central processing unit (CPU) complex comprising one or more processors;
• one or more component blocks coupled to the CPU complex, wherein the one or more component blocks are configured to implement one or more operational features of the integrated circuit other than a CPU feature;
• and
• a debug control unit coupled to the CPU complex and the one or more component blocks, wherein the debug control unit is configured to monitor for debug events in the CPU complex and the one or more component blocks, and wherein the debug control unit is configured to halt the CPU complex and the one or more component blocks responsive to detecting a specified one or more debug events, and wherein the debug control unit is programmable with a delay from the detection of the specified one or more debug events, and wherein the debug control unit is configured to halt the CPU complex and the one or more component blocks responsive to the expiration of the delay.

In an integrated circuit comprising a central processing unit (CPU) complex comprising one or more processors;

• one or more component blocks coupled to the CPU complex, wherein the one or more component blocks are configured to implement one or more operational features of the integrated circuit other than the CPU feature;
• a plurality of local debug control units, wherein one of the plurality of local debug control units is included in the CPU complex and each other one of the plurality of local debug control units is included in a respective one of the one or more component blocks;
• and a debug control unit coupled to the plurality of local debug control units in a ring;
• a method comprising:
• monitoring for debug events in the corresponding CPU complex or component block by the plurality of local debug control units;
• detecting, in a first local debug unit of the plurality of debug units, a first debug event;
• transmitting, by the first local debug unit, an indication of the first debug event on the ring;
• receiving, in a second debug unit, the indication of the first debug event;
• and
• triggering, in the second debug unit, monitoring for a second debug event responsive to receiving the indication of the first debug event.