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US 8,799,708 B2Granted
Information processing apparatus, control device, and abnormal unit determination method
AssigneeFujitsu Limited
InventorShigeo Kojina
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AssigneeFujitsu Limited
InventorShigeo Kojina
Estimating the term…
An information processing apparatus determines an abnormal unit by: determining whether or not there is an abnormal point in access to a slave unit by a first master unit that controls a plurality of slave units connected by a serial bus; requesting a second master unit having redundancy with the first master unit to access a specific slave unit when the abnormal point is determined to exist in access to the specific slave unit in the determining; and determining a unit having an abnormality by use of an access result relating to the abnormal point determined to have an abnormality in the determining and an access result indicating a result of the request made in the requesting.
An information processing apparatus comprising:
A control device configured to control a plurality of slave units comprising:
A method for determining an abnormal unit executed by an information processing apparatus including a first master unit and a second master unit, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Error detection or correction of the data by redundancy in hardware: using active fault-masking, e.g. by switching out faulty elements or by…
Where interconnections or communication control functionality are redundant: using redundant communication controllers
Where interconnections or communication control functionality are redundant: using redundant communication media
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus
About 5 years 9 months of term left · ends 14 Jul 2032 (estimated)
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2011-063404, filed on Mar. 22, 2011, the entire contents of which are incorporated herein by reference.
The embodiment discussed herein is directed to, for example, an information processing apparatus.
An inter-integrated circuit (I2C) bus is a two-wire bidirectional serial bus and has a simple structure with two signal lines of a serial clock and serial data. Such a simple structure allows the I2C bus to be readily introduced.
FIG. 1 is a functional block diagram illustrating a configuration of an I2C bus device according to an embodiment of the present invention;
FIG. 2A is a diagram illustrating a connection of an I2C bus between units to determine an abnormal unit according to the embodiment;
FIG. 2B is a diagram illustrating a method for determining the abnormal unit according to the embodiment;
Preferred embodiments of the present invention will be explained with reference to accompanying drawings. In the following description, the embodiment is applied to an I2C bus device serving as the information processing apparatus including an I2C bus. However, the embodiment of the present invention is not limited thereto.
According to an embodiment, when there is an abnormality in any of I2C units connected to an I2C bus during operation of an I2C bus device, the I2C bus device can determine which I2C unit has an abnormality. In the I2C bus device, an I2C unit on a master side and an I2C unit on a slave side are connected one-to-one instead of one-to-many by the same I2C bus so that the unit having the abnormality is determined. In the I2C bus device, moreover, two I2C units are disposed on the master side and access the I2C unit on the slave side in a separate manner through different paths. Accordingly, the I2C bus device can determine the I2C unit having the abnormality by integration of each of the access results.
FIG. 2A is a diagram illustrating a connection of an I2C bus between units to determine an abnormal unit according to the embodiment. As illustrated in FIG. 2A, I2C master units 1A and 1B are connected one-to-one with an I2C slave unit 3 by substantially the same I2C bus.