Control of digital voltage and frequency scaling operating points

An apparatus for generating a clock signal to be supplied to electronic circuitry, the apparatus comprising:

• circuitry configured to generate, based on which one of a plurality of application use cases capable of being carried out by the electronic circuitry is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points;
• circuitry configured to generate, based on a present speed requirement of the electronic circuitry, a second signal that indicates a second selected one of the plurality of clock signal operating points;
• circuitry configured to generate, based on the first and second signals, a third signal that indicates which of the plurality of clock signal operating points should be active, wherein the clock signal operating point indicated by the third signal is whichever one of the clock signal operating points indicated by the first and second signals is associated with a higher clock signal frequency;
• and
• circuitry configured to use the third signal to control generation of a clock signal having the operating point indicated by the third signal,
• wherein for any given one of the application use cases, the present speed requirement need not remain constant for the duration of the given one of the application use cases,
• wherein the first selected one of the plurality of clock signal operating points can be associated with a higher clock signal frequency than a clock signal frequency associated with the second selected one of the plurality of clock signal operating points,
• wherein the second selected one of the plurality of clock signal operating points can be associated with a higher clock signal frequency than a clock signal frequency associated with the first selected one of the plurality of clock signal operating points, and
• wherein the circuitry configured to generate the second signal is configured to respond to changes in the present speed requirement that take place during the given one of the application use cases by changing the state of the second signal while the first signal remains constant during the given one of the application use cases, whereby an average clock frequency during the given one of the application use cases is not equal to any one of a plurality of clock frequencies that respectively correspond to the clock signal operating points.