Information handling system with processing system, low-power processing system and shared resources

A chipset comprising:

• a low power processor configured to be disabled during operation of a processing system in an information handling system;
• a processor configured to be disabled during operation of a low power processing system in the information handling system;
• a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system;
• and
• a video multiplexing layer powered by a power system, the video multiplexing layer configured to receive a processing system video input and a low power processing system video input, and to up-scale a video output by combining the processing system video input with the low power processing system video input prior to outputting the video output.

An information handling system comprising:

• a chipset including:
• a low power processor configured to be disabled during operation of a processing system in an information handling system;
• a processor configured to be disabled during operation of a low power processing system in the information handling system;
• and
• a switching module, the switching module configured to enable the processor to access one or more shared resources during operation of the processing system, and configured to enable the low power processor to access one or more non-shared resources during operation of the low power processing system;
• and
• a video raster coupled to the chipset and operable to be accessed as a shared video output resource by the processor and by the low power processor.