Dynamic power optimization for computing devices

A computing device configured to optimize object code during execution for improved power savings, comprising:

• means for receiving compiled binary object code in system software;
• means for analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;
• means for sensing a change in a connection from an initial power source to a different power source;
• means for performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code in response to sensing the change in the connection from the initial power source to the different power source;
• and
• means for executing the power optimized object code on a processor of the computing device.

A computing device, comprising:

• a memory;
• and
• one or more processors coupled to the memory, wherein the one or more processors are configured with processor-executable instructions so the computing device performs operations comprising:
• receiving compiled binary object code in system software;
• analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;
• sensing a change in a connection from an initial power source to a different power source;
• performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code in response to sensing the change in the connection from the initial power source to the different power source;
• and
• executing the power optimized object code.

A non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform operations for optimizing object code for power savings during execution on a computing device, the operations comprising:

• receiving compiled binary object code in system software;
• analyzing the received object code in a dynamic binary translator operating at the machine layer to identify code segments that can be optimized for power savings;
• sensing a change in a connection from an initial power source to a different power source;
• performing in the dynamic binary translator an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code;
• and
• executing the power optimized object code on a processor of the computing device in response to sensing the change in the connection from the initial power source to the different power source.

A system on chip, comprising:

• a memory;
• and one or more cores coupled to the memory, wherein the one or more cores are configured with processor-executable instructions so the system on chip performs operations comprising:
• receiving in an operating system compiled binary object code;
• analyzing the received object code in a dynamic binary translator process operating at the machine layer to identify code segments that can be optimized for power savings;
• sensing a change in a connection from an initial power source to a different power source;
• performing in the dynamic binary translator process an instruction-sequence to instruction-sequence translation of the received object code to generate power optimized object code in response to sensing the change in the connection from the initial power source to the different power source;
• and
• executing the power optimized object code.