Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates

A method to support energy conservation techniques in a processor, comprising:

• receiving a request from an operating system, wherein the request includes a first power saving state into which the processor is to be placed,
• demoting the processor to a second power saving state, which is a shallower power saving state than the first power saving state if a low activity period of the processor overlaps with a burst of high interrupt rate, and
• un-demoting the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,
• wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from the operating system.

A computer system to support energy conservation techniques, comprising:

• a plurality of input-output devices,
• a logic coupled to the plurality of input-output devices,
• a display device coupled to the logic,
• a machine readable storage medium coupled to the logic, and
• a processor coupled to the logic, wherein the processor further includes,
• a plurality of processing cores,
• an uncore area, and
• a power management unit, wherein the power management unit to,
• receive a request from an operating system, wherein the request includes
• a first power saving state into which the processor is to be placed,
• demote the processor to a second power saving state, which is a shallower power saving state than the first power saving state if a low activity period of the processor overlaps with a burst of high interrupt rate, and
• un-demote the processor to a third power saving state, which is a deeper power saving state than the first power saving state in response to determining that an interrupt rate is low,
• wherein the power management unit to proactively transition the processor into deeper power saving states even in the absence of a wake-up interrupt from the operating system.