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US 8,799,673 B2Granted
Seamlessly encrypting memory regions to protect against hardware-based attacks
AssigneeIntel Corporation
InventorsUday R. Savagaonkar, Ravi Sahita, David Durham, Men Long
Life of this patent
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Abstract
Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction.
Claims20
An apparatus comprising:
- a decoder to decode one of a memory read and a memory write transaction on a connection between a first hardware component and a second hardware component in the apparatus, the transaction from a processor to a first address, the first address in a memory-mapped input/output space;
- control logic to, in response to the decoder determining that the first address is within a protected region, redirect the transaction from the first address to second address, the second address in a system memory;
- and
- cryptographic logic to operate on data for the transaction.
1 more element
A method comprising:
- decoding one of a memory read and a memory write transaction on a connection between a first hardware component and a second hardware component in a system, the transaction from a processor to a first address, the first address in a memory-mapped input/output space;
- performing, in response to the decoding determining that the first address is within a protected region, a cryptographic operation on data for the transaction;
- and
- redirecting, in response to the decoding determining that the first address is within the protected region, the transaction from the first address to second address, the second address in a system memory.
1 more element
A system comprising:
- a processor;
- a system memory;
- and
- a memory encryption engine including:
- a decoder to decode one of a memory read and a memory write transaction on a connection between a first component and a second component in the system, the transaction from the processor to a first address, the first address in a memory-mapped input/output space;
- control logic to, in response to the decoder determining that the first address is within a protected region, redirect the transaction from the first address to second address, the second address in the system memory;
- and
- cryptographic logic to operate on data for the transaction.
5 more elements
Dependencies are inferred from the claim text.