Configurable device interfaces
AssigneeTilera Corporation
InventorsPatrick Robert Griffin, Carl G. Ramey
Life of this patent
Estimating the term…
Abstract
Coupling a device to a multicore computing system that includes multiple cores that each include a processor includes sending messages to access memory coupled to at least one of the multiple cores, the memory having an address space, and the messages including a virtual address. An interface is provided for coupling the device to the multicore computing system in a shim that: transmits or receives messages on the communication network among the processors to or from the coupled device, and translates virtual addresses to physical addresses of the address space in response to receiving the messages over the communication network that include a virtual address.
Claims17
An apparatus, comprising:
- a multicore computing system that includes multiple tiles each tile including a processor and a switch;
- a communication network among the processors that is configurable by the switch and processor of each tile;
- memory coupled to at least one of the multiple tiles, the memory having an address space;
- a hardware shim that is external to the multiple tiles the shim configured to couple an external device to the multicore computing system, the hardware shim comprising:
- circuitry to couple the hardware shim to one of the multiple tiles;
- circuitry configured to transmit or receive messages on the communication network to or from a coupled device;
- and
- circuitry including a translation lookaside buffer to store translated physical addresses to translate virtual addresses to physical addresses of the address space of the memory in response to receiving messages over the communication network that include a virtual address and that are received at the shim such that packet data is directly placed into the memory that is accessed with physical addresses of the memory.
An apparatus, comprising:
- a multicore computing system that includes multiple tiles each tile including a processor and a switch;
- a communication network among the processors that is configurable by the switch and processor of each tile;
- memory coupled to at least one of the multiple tiles, the memory having an address space;
- a hardware shim that is external to the multiple tiles the shim configured to couple an external device to the multicore computing system, the hardware shim comprising:
- circuitry to couple the hardware shim to one of the multiple tiles;
- circuitry configured to transmit messages to a coupled device and encode messages into packets, and to receive messages from the coupled device and post received packets to a software routine running on a processor of a tile connected to the shim via the communication network;
- and
- circuitry including a translation lookaside buffer to store translated physical addresses to translate virtual addresses to physical addresses of the address space of the memory in response to receiving messages over the communication network that include a virtual address and that are received at the shim such that packet data is directly placed into the memory that is accessed with physical addresses of the memory.
A method for coupling a device to a multicore computing system that includes multiple tiles each tile including a processor and a switch a communication network among the processors that is configurable by the switch and processor of each tile and memory coupled to at least one of the multiple tiles, the memory having an address space, the method comprising:
- configuring a hardware shim that is external to the multiple tiles to couple an external device to the multicore computing system;
- coupling the hardware shim to one of the multiple tiles;
- configuring the hardware shim to transmit or receive messages on the communication network to or from a coupled device;
- translating using a translation lookaside buffer virtual addresses to physical addresses of the address space of the memory in response to receiving messages over the communication network that include a virtual address and that are received at the shim such that packet data is directly placed into the memory that is accessed with physical addresses of the memory;
- and
- storing received messages at the translated physical addresses of the memory.
Dependencies are inferred from the claim text.