Hierarchical reconfigurable computer architecture

A portable media device comprising at least one reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels comprise:

• a first level comprising a first computation block comprising a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting means, each computing node comprising:
• an input port;
• a functional unit;
• and
• an output port;
• the first connecting means configured to interconnect the plurality of computing nodes, wherein each computing node of the plurality of computing nodes further comprises an instruction memory configured to dynamically control the first connecting means during execution of instructions;
• and
• a second level comprising a second computation block comprising:
• a second data input;
• a second data output;
• and
• a plurality of said first computation blocks interconnected by a second connecting means for connecting a selected one of said first data output of each of said first computation blocks and said second data input to each of said first data inputs and for connecting a selected one of said first data outputs to said second data output.

A method of mapping a required task onto the physical resources of a reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, a first level comprising a cluster comprising a plurality of interconnected computing nodes each comprising a functional unit, and a second level comprising an interconnected plurality of said clusters, said method comprising:

• partitioning said task into subtasks each comprising a plurality of operations;
• assigning each of said subtasks to one of said clusters;
• assigning the operations of each subtask to the computing nodes in each cluster;
• and
• scheduling the operations in the computing nodes and performing fine routing between computing nodes, wherein said step of scheduling the operations and performing fine routing comprises reducing a number of connections between clusters by providing a connection between a first computing node in a first cluster and a second computing node in a second cluster via a third computing node in said first cluster.

A method of mapping a required task onto the physical resources of a hierarchical reconfigurable computer architecture having N levels, where N is an integer value greater than one, a first level comprising a cluster comprising a plurality of interconnected computing nodes, and a second level comprising a plurality of interconnected clusters, said method comprising:

• determining that a new connection is required between a first computing node in a first cluster and a second computing node in a second cluster;
• determining whether a connection already exists between a third computing node in said first cluster and said second cluster;
• if said connection already exists connecting said first computing node to said second computing node via said third computing node;
• and
• if no connection exists between said third computing node and said second cluster, creating a connection between said first computing node and said second computing node, and connecting at least one other computing node of said first cluster to said second cluster via said first computing node.

A reconfigurable hierarchical computer architecture comprising:

• in a first level of the hierarchical architecture, at least two computing nodes interconnected by a first level connection device to form a cluster, each computing node comprising at least one input port, a functional unit and an output port;
• and
• in a second level of the hierarchical architecture, at least two clusters interconnected by a second level connection device to form a computing sub-block, each cluster having an input port and an output port, wherein each computing node further comprises:
• an input buffer associated with the at least one input port;
• a register file configured to receive an output of the functional unit;
• a selector configured to receive inputs from the input buffer and the register file and to supply data to the functional unit and to the output port;
• and
• an instruction memory configured to control the input buffer, the register file and the selector.