Translation table control
AssigneeArm Limited
InventorRichard Roy Grisenthwaite
Life of this patent
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Abstract
Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables 28, 32, 36, 38, 40, 42. A page size variable S is used to control the memory address translation circuitry 14 to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 62.
Claims11
Apparatus for processing data comprising:
- memory address translation circuitry configured to perform a top down page table walk operation to translate a virtual memory address to a physical memory address using translation data stored in a hierarchy of translation tables;
- wherein
- said translation data specifies translations between pages of 2N contiguous bytes of virtual memory addresses and corresponding pages of 2N contiguous bytes of physical memory addresses, where N is a positive integer;
- said hierarchy of translation tables comprises translation tables of 2N contiguous bytes in size such that a complete translation table is stored within one page of said physical memory;
- and
- said memory address translation circuitry is responsive to a page size variable specifying a current value of N to control said memory address translation circuitry to operate with a selected size of pages of physical memory addresses, pages of virtual memory addresses and translation tables, wherein a predetermined portion of said virtual address extending from a most significant bit end of said virtual address is given a fixed translation to a corresponding portion of said physical address without requiring a page table walk.
Apparatus for processing data comprising:
- memory address translation means for performing a top down page table walk operation to translate a virtual memory address to a physical memory address using translation data stored in a hierarchy of translation tables;
- wherein
- said translation data specifies translations between pages of 2N contiguous bytes of virtual memory addresses and corresponding pages of 2N contiguous bytes of physical memory addresses, where N is a positive integer;
- said hierarchy of translation tables comprises translation tables of 2N contiguous bytes in size such that a complete translation table is stored within one page of said physical memory;
- and
- said memory address translation means is responsive to a page size variable specifying a current value of N to control said memory address translation circuitry to operate with a selected size of pages of physical memory addresses, pages of virtual memory addresses and translation tables, wherein a predetermined portion of said virtual address extending from a most significant bit end of said virtual address is given a fixed translation to a corresponding portion of said physical address without requiring a page table walk.
A method of processing data comprising the steps of:
- performing a top down page table walk operation to translate a virtual memory address to a physical memory address using translation data stored in a hierarchy of translation tables;
- wherein
- said translation data specifies translations between pages of 2N contiguous bytes of virtual memory addresses and corresponding pages of 2N contiguous bytes of physical memory addresses, where N is a positive integer;
- said hierarchy of translation tables comprises translation tables of 2N contiguous bytes in size such that a complete translation table is stored within one page of said physical memory;
- and
- operating with a selected size of pages of physical memory addresses, pages of virtual memory addresses and translation tables in response to a page size variable specifying a current value of N, wherein a predetermined portion of said virtual address extending from a most significant bit end of said virtual address is given a fixed translation to a corresponding portion of said physical address without requiring a page table walk.
Dependencies are inferred from the claim text.