Redundancy loading efficiency
AssigneeSpansion LLC
InventorsWei-Kent Ong, Jih-Hong Beh, Sei-Wei Henry Lau, Oon-Poh Ang
Life of this patent
Estimating the term…
Abstract
A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
Claims31
A method comprising:
- loading a first portion of a set of redundancy data into a register of a microcontroller for each redundant sector of a plurality of redundant sectors, wherein the register is loaded with a plurality of first portions of sets of redundancy data, a first portion of a set of redundancy data for each redundant sector;
- loading a second portion of the set of redundancy data into the register for each redundant sector of the plurality of redundant sectors, wherein the register is loaded with a plurality of second portions of redundancy data, a second portion of the set of redundancy data for each redundant sector, wherein loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method comprising:
- loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors, wherein the register is loaded with a plurality of first portions of sets of redundancy data, a first portion of a set of redundancy data for each redundant sector;
- loading a second portion of the set of redundancy data into the register for each redundant sector of the plurality of redundant sectors, wherein the register is loaded with a plurality of second portions of redundancy data, a second portion of the set of redundancy data for each redundant sector, wherein loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
A system comprising:
- a processor comprising a register;
- a volatile memory;
- a nonvolatile memory;
- and
- a look-up table, wherein upon powering the nonvolatile memory, redundancy data in the look-up table is loaded into the register, wherein loading the redundancy data comprises:
- loading a first portion of a set of redundancy data into the volatile memory for each redundant sector of a plurality of redundant sectors in the nonvolatile memory, wherein the register is loaded with a plurality of first portions of sets of redundancy data, a first portion of a set of redundancy data for each redundant sector;
- loading a second portion of the set of redundancy data into the volatile memory for each redundant sector of the plurality of redundant sectors in the nonvolatile memory, wherein the register is loaded with a plurality of second portions of redundancy data, a second portion of the set of redundancy data for each redundant sector, wherein loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors in the nonvolatile memory.
Dependencies are inferred from the claim text.