Method and apparatus for implementing multi-processor memory coherency

A multi-processor device, comprising a first cluster, a second cluster, a Level-2 (L2) cache of the first cluster, and an L2 cache of the second cluster, wherein:

• the L2 cache of the first cluster is connected to an Accelerator Coherency Port (ACP) of a Level-1 (L1) cache of the second cluster;
• and the L2 cache of the first cluster is configured to:
• receive a control signal of the first cluster for reading first data;
• read the first data in the L1 cache of the second cluster through the ACP of the L1 cache of the second cluster if the first data is currently maintained by the second cluster;
• and provide the first data read to the first cluster for processing, wherein:
• the L2 cache of the first cluster is further configured to:
• obtain a result of the first data processed by the first cluster;
• write the result of the first data processed by the first cluster into the L1 cache or L2 cache of the second cluster through the ACP of the L1 cache of the second cluster;
• or, buffer the result of the first data processed by the first cluster into the L2 cache of the first cluster;
• and
• wherein:
• the L2 cache of the first cluster comprises:
• a first receiving module, configured to receive the control signal of the first cluster for reading the first data, wherein an operation attribute of the control signal is “non-cacheable”;
• a first reading module, configured to send a control signal for reading the first data to the L1 cache of the second cluster through the ACP of the L1 cache of the second cluster when the first data is currently maintained by the second cluster, wherein the operation attribute of the control signal is “cacheable”;
• and read the first data in the L1 cache of the second cluster;
• and a first providing module, configured to provide the first data read by the first reading module to the first cluster for processing.