Memory controlling device
AssigneeSony Corporation
InventorTakahiro Ikarashi
Life of this patent
Estimating the term…
Abstract
A memory controlling device that includes a request generating section for generating a memory request, a row selecting information retaining section that retains data relative to row address information, a column selecting information retaining section that retains data relative to column address information, a memory bank information for managing section operation states of the memory device, a command generating section for generating operation commands, and a command aligning section that synchronizes the operation commands with the clock.
Claims18
A memory controlling device comprising:
- a request generating section configured to generate memory requests from a data access request to a memory controlled in each of memory banks;
- a row selecting information retaining section configured to retain a plurality of opcodes, memory bank numbers specifying said memory banks, and row addresses specifying row addresses in said memory banks in said memory requests as row selecting information while maintaining input order of said memory requests;
- a column selecting information retaining section configured to separately retain a plurality of said opcodes, said memory bank numbers, column addresses specifying column addresses in said memory banks, and data lengths of data to be accessed according to said memory requests in said memory requests as column selecting information while maintaining the input order of said memory requests;
- a memory bank information managing section configured to manage a state of operation of said memory as memory bank information for each of said memory banks;
- a command generating section configured to generate a plurality of commands designating operation related to said memory banks at a frequency lower than frequency of a memory clock of said memory on a basis of said row selecting information, said column selecting information, and said memory bank information;
- and
- a command aligning section configured to align said plurality of generated commands in synchronism with said memory clock.
A memory controlling device comprising:
- an operation designation supplying section configured to supply opcodes, column addresses, and row addresses for generating commands designating operation for a memory;
- a row selecting information retaining section configured to retain said row addresses for generating said commands as row selecting information;
- a column selecting information retaining section configured to separately retain said opcodes and said column addresses as column selecting information;
- a memory information managing section configured to manage memory information retaining a row address in an active state in said memory and timing in which said commands can be generated;
- a command generating section configured to generate a plurality of said commands at a frequency lower than frequency of a memory clock of said memory by generating a command to read row data corresponding to said row address from said memory among said commands on a basis of said memory information and said row selecting information and a command to read data corresponding to one of said column addresses from said row data among said commands on a basis of said memory information and said column selecting information;
- and
- a command aligning section configured to align said plurality of generated commands in synchronism with said memory clock.
A memory controlling device comprising:
- request generating means for generating memory requests from a data access request to a memory controlled in each of memory banks;
- row selecting information retaining means for retaining a plurality of opcodes, memory bank numbers specifying said memory banks, and row addresses specifying row addresses in said memory banks in said memory requests as row selecting information while maintaining input order of said memory requests;
- column selecting information retaining means for separately retaining a plurality of said opcodes, said memory bank numbers, column addresses specifying column addresses in said memory banks, and data lengths of data to be accessed according to said memory requests in said memory requests as column selecting information while maintaining the input order of said memory requests;
- memory bank information managing means for managing a state of operation of said memory as memory bank information for each of said memory banks;
- command generating means for generating a plurality of commands designating operation related to said memory banks at a frequency lower than frequency of a memory clock of said memory on a basis of said row selecting information, said column selecting information, and said memory bank information;
- and
- command aligning means for aligning said plurality of generated commands in synchronism with said memory clock.
A memory controlling device comprising:
- operation designation supplying means for supplying opcodes, column addresses, and row addresses for generating commands designating operation for a memory;
- row selecting information retaining means for retaining said row addresses for generating said commands as row selecting information;
- column selecting information retaining means for separately retaining said opcodes and said column addresses as column selecting information;
- memory information managing means for managing memory information retaining a row address in an active state in said memory and timing in which said commands can be generated;
- command generating means for generating a plurality of said commands at a frequency lower than frequency of a memory clock of said memory by generating a command to read row data corresponding to said row address from said memory among said commands on a basis of said memory information and said row selecting information and a command to read data corresponding to one of said column addresses from said row data among said commands on a basis of said memory information and said column selecting information;
- and
- command aligning means for aligning said plurality of generated commands in synchronism with said memory clock.
Dependencies are inferred from the claim text.